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Portapack-Carnage
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Macros | |
| #define | ADC_ISR_AWD ((uint32_t)0x00000080) |
| #define | ADC_ISR_OVR ((uint32_t)0x00000010) |
| #define | ADC_ISR_EOSEQ ((uint32_t)0x00000008) |
| #define | ADC_ISR_EOC ((uint32_t)0x00000004) |
| #define | ADC_ISR_EOSMP ((uint32_t)0x00000002) |
| #define | ADC_ISR_ADRDY ((uint32_t)0x00000001) |
| #define | ADC_ISR_EOS ADC_ISR_EOSEQ |
| #define | ADC_IER_AWDIE ((uint32_t)0x00000080) |
| #define | ADC_IER_OVRIE ((uint32_t)0x00000010) |
| #define | ADC_IER_EOSEQIE ((uint32_t)0x00000008) |
| #define | ADC_IER_EOCIE ((uint32_t)0x00000004) |
| #define | ADC_IER_EOSMPIE ((uint32_t)0x00000002) |
| #define | ADC_IER_ADRDYIE ((uint32_t)0x00000001) |
| #define | ADC_IER_EOSIE ADC_IER_EOSEQIE |
| #define | ADC_CR_ADCAL ((uint32_t)0x80000000) |
| #define | ADC_CR_ADSTP ((uint32_t)0x00000010) |
| #define | ADC_CR_ADSTART ((uint32_t)0x00000004) |
| #define | ADC_CR_ADDIS ((uint32_t)0x00000002) |
| #define | ADC_CR_ADEN ((uint32_t)0x00000001) |
| #define | ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) |
| #define | ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) |
| #define | ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) |
| #define | ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) |
| #define | ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) |
| #define | ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) |
| #define | ADC_CFGR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) |
| #define | ADC_CFGR1_DISCEN ((uint32_t)0x00010000) |
| #define | ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) |
| #define | ADC_CFGR1_WAIT ((uint32_t)0x00004000) |
| #define | ADC_CFGR1_CONT ((uint32_t)0x00002000) |
| #define | ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) |
| #define | ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) |
| #define | ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) |
| #define | ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) |
| #define | ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) |
| #define | ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) |
| #define | ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) |
| #define | ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) |
| #define | ADC_CFGR1_ALIGN ((uint32_t)0x00000020) |
| #define | ADC_CFGR1_RES ((uint32_t)0x00000018) |
| #define | ADC_CFGR1_RES_0 ((uint32_t)0x00000008) |
| #define | ADC_CFGR1_RES_1 ((uint32_t)0x00000010) |
| #define | ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) |
| #define | ADC_CFGR1_DMACFG ((uint32_t)0x00000002) |
| #define | ADC_CFGR1_DMAEN ((uint32_t)0x00000001) |
| #define | ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT |
| #define | ADC_CFGR2_JITOFFDIV4 ((uint32_t)0x80000000) |
| #define | ADC_CFGR2_JITOFFDIV2 ((uint32_t)0x40000000) |
| #define | ADC_SMPR1_SMPR ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMPR_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMPR_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMPR_2 ((uint32_t)0x00000004) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) |
| #define | ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) |
| #define | ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) |
| #define | ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) |
| #define | ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) |
| #define | ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) |
| #define | ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) |
| #define | ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) |
| #define | ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) |
| #define | ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) |
| #define | ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) |
| #define | ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) |
| #define | ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) |
| #define | ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) |
| #define | ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) |
| #define | ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) |
| #define | ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) |
| #define | ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) |
| #define | ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_CCR_VBATEN ((uint32_t)0x01000000) |
| #define | ADC_CCR_TSEN ((uint32_t)0x00800000) |
| #define | ADC_CCR_VREFEN ((uint32_t)0x00400000) |
| #define | CEC_CR_CECEN ((uint32_t)0x00000001) |
| #define | CEC_CR_TXSOM ((uint32_t)0x00000002) |
| #define | CEC_CR_TXEOM ((uint32_t)0x00000004) |
| #define | CEC_CFGR_SFT ((uint32_t)0x00000007) |
| #define | CEC_CFGR_RXTOL ((uint32_t)0x00000008) |
| #define | CEC_CFGR_BRESTP ((uint32_t)0x00000010) |
| #define | CEC_CFGR_BREGEN ((uint32_t)0x00000020) |
| #define | CEC_CFGR_LREGEN ((uint32_t)0x00000040) |
| #define | CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) |
| #define | CEC_CFGR_SFTOPT ((uint32_t)0x00000100) |
| #define | CEC_CFGR_OAR ((uint32_t)0x7FFF0000) |
| #define | CEC_CFGR_LSTN ((uint32_t)0x80000000) |
| #define | CEC_TXDR_TXD ((uint32_t)0x000000FF) |
| #define | CEC_TXDR_RXD ((uint32_t)0x000000FF) |
| #define | CEC_ISR_RXBR ((uint32_t)0x00000001) |
| #define | CEC_ISR_RXEND ((uint32_t)0x00000002) |
| #define | CEC_ISR_RXOVR ((uint32_t)0x00000004) |
| #define | CEC_ISR_BRE ((uint32_t)0x00000008) |
| #define | CEC_ISR_SBPE ((uint32_t)0x00000010) |
| #define | CEC_ISR_LBPE ((uint32_t)0x00000020) |
| #define | CEC_ISR_RXACKE ((uint32_t)0x00000040) |
| #define | CEC_ISR_ARBLST ((uint32_t)0x00000080) |
| #define | CEC_ISR_TXBR ((uint32_t)0x00000100) |
| #define | CEC_ISR_TXEND ((uint32_t)0x00000200) |
| #define | CEC_ISR_TXUDR ((uint32_t)0x00000400) |
| #define | CEC_ISR_TXERR ((uint32_t)0x00000800) |
| #define | CEC_ISR_TXACKE ((uint32_t)0x00001000) |
| #define | CEC_IER_RXBRIE ((uint32_t)0x00000001) |
| #define | CEC_IER_RXENDIE ((uint32_t)0x00000002) |
| #define | CEC_IER_RXOVRIE ((uint32_t)0x00000004) |
| #define | CEC_IER_BREIEIE ((uint32_t)0x00000008) |
| #define | CEC_IER_SBPEIE ((uint32_t)0x00000010) |
| #define | CEC_IER_LBPEIE ((uint32_t)0x00000020) |
| #define | CEC_IER_RXACKEIE ((uint32_t)0x00000040) |
| #define | CEC_IER_ARBLSTIE ((uint32_t)0x00000080) |
| #define | CEC_IER_TXBRIE ((uint32_t)0x00000100) |
| #define | CEC_IER_TXENDIE ((uint32_t)0x00000200) |
| #define | CEC_IER_TXUDRIE ((uint32_t)0x00000400) |
| #define | CEC_IER_TXERRIE ((uint32_t)0x00000800) |
| #define | CEC_IER_TXACKEIE ((uint32_t)0x00001000) |
| #define | COMP_CSR_COMP1EN ((uint32_t)0x00000001) |
| #define | COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) |
| #define | COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) |
| #define | COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) |
| #define | COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) |
| #define | COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) |
| #define | COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) |
| #define | COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) |
| #define | COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) |
| #define | COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) |
| #define | COMP_CSR_COMP1POL ((uint32_t)0x00000800) |
| #define | COMP_CSR_COMP1HYST ((uint32_t)0x00003000) |
| #define | COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) |
| #define | COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) |
| #define | COMP_CSR_COMP1OUT ((uint32_t)0x00004000) |
| #define | COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) |
| #define | COMP_CSR_COMP2EN ((uint32_t)0x00010000) |
| #define | COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) |
| #define | COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) |
| #define | COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) |
| #define | COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) |
| #define | COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) |
| #define | COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) |
| #define | COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) |
| #define | COMP_CSR_WNDWEN ((uint32_t)0x00800000) |
| #define | COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) |
| #define | COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) |
| #define | COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) |
| #define | COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) |
| #define | COMP_CSR_COMP2POL ((uint32_t)0x08000000) |
| #define | COMP_CSR_COMP2HYST ((uint32_t)0x30000000) |
| #define | COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) |
| #define | COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) |
| #define | COMP_CSR_COMP2OUT ((uint32_t)0x40000000) |
| #define | COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | CRC_CR_REV_IN ((uint32_t)0x00000060) |
| #define | CRC_CR_REV_IN_0 ((uint32_t)0x00000020) |
| #define | CRC_CR_REV_IN_1 ((uint32_t)0x00000040) |
| #define | CRC_CR_REV_OUT ((uint32_t)0x00000080) |
| #define | CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) |
| #define | DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) |
| #define | DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_IMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_IMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_IMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_IMR_MR25 ((uint32_t)0x02000000) |
| #define | EXTI_IMR_MR27 ((uint32_t)0x08000000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_EMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_EMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_EMR_MR25 ((uint32_t)0x02000000) |
| #define | EXTI_EMR_MR27 ((uint32_t)0x08000000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000001) |
| #define | FLASH_ACR_PRFTBE ((uint32_t)0x00000010) |
| #define | FLASH_ACR_PRFTBS ((uint32_t)0x00000020) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_FKEY1 ((uint32_t)0x45670123) |
| #define | FLASH_FKEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEY1 ((uint32_t)0x45670123) |
| #define | FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) |
| #define | FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) |
| #define | FLASH_OBR_USER ((uint32_t)0x00003700) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) |
| #define | FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) |
| #define | FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) |
| #define | FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 |
| #define | FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR |
| #define | FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) |
| #define | OB_RDP_RDP ((uint32_t)0x000000FF) |
| #define | OB_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | OB_USER_USER ((uint32_t)0x00FF0000) |
| #define | OB_USER_nUSER ((uint32_t)0xFF000000) |
| #define | OB_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | OB_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | OB_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) |
| #define | GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) |
| #define | GPIO_BRR_BR_0 ((uint32_t)0x00000001) |
| #define | GPIO_BRR_BR_1 ((uint32_t)0x00000002) |
| #define | GPIO_BRR_BR_2 ((uint32_t)0x00000004) |
| #define | GPIO_BRR_BR_3 ((uint32_t)0x00000008) |
| #define | GPIO_BRR_BR_4 ((uint32_t)0x00000010) |
| #define | GPIO_BRR_BR_5 ((uint32_t)0x00000020) |
| #define | GPIO_BRR_BR_6 ((uint32_t)0x00000040) |
| #define | GPIO_BRR_BR_7 ((uint32_t)0x00000080) |
| #define | GPIO_BRR_BR_8 ((uint32_t)0x00000100) |
| #define | GPIO_BRR_BR_9 ((uint32_t)0x00000200) |
| #define | GPIO_BRR_BR_10 ((uint32_t)0x00000400) |
| #define | GPIO_BRR_BR_11 ((uint32_t)0x00000800) |
| #define | GPIO_BRR_BR_12 ((uint32_t)0x00001000) |
| #define | GPIO_BRR_BR_13 ((uint32_t)0x00002000) |
| #define | GPIO_BRR_BR_14 ((uint32_t)0x00004000) |
| #define | GPIO_BRR_BR_15 ((uint32_t)0x00008000) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_TXIE ((uint32_t)0x00000002) |
| #define | I2C_CR1_RXIE ((uint32_t)0x00000004) |
| #define | I2C_CR1_ADDRIE ((uint32_t)0x00000008) |
| #define | I2C_CR1_NACKIE ((uint32_t)0x00000010) |
| #define | I2C_CR1_STOPIE ((uint32_t)0x00000020) |
| #define | I2C_CR1_TCIE ((uint32_t)0x00000040) |
| #define | I2C_CR1_ERRIE ((uint32_t)0x00000080) |
| #define | I2C_CR1_DFN ((uint32_t)0x00000F00) |
| #define | I2C_CR1_ANFOFF ((uint32_t)0x00001000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00002000) |
| #define | I2C_CR1_TXDMAEN ((uint32_t)0x00004000) |
| #define | I2C_CR1_RXDMAEN ((uint32_t)0x00008000) |
| #define | I2C_CR1_SBC ((uint32_t)0x00010000) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) |
| #define | I2C_CR1_WUPEN ((uint32_t)0x00040000) |
| #define | I2C_CR1_GCEN ((uint32_t)0x00080000) |
| #define | I2C_CR1_SMBHEN ((uint32_t)0x00100000) |
| #define | I2C_CR1_SMBDEN ((uint32_t)0x00200000) |
| #define | I2C_CR1_ALERTEN ((uint32_t)0x00400000) |
| #define | I2C_CR1_PECEN ((uint32_t)0x00800000) |
| #define | I2C_CR2_SADD ((uint32_t)0x000003FF) |
| #define | I2C_CR2_RD_WRN ((uint32_t)0x00000400) |
| #define | I2C_CR2_ADD10 ((uint32_t)0x00000800) |
| #define | I2C_CR2_HEAD10R ((uint32_t)0x00001000) |
| #define | I2C_CR2_START ((uint32_t)0x00002000) |
| #define | I2C_CR2_STOP ((uint32_t)0x00004000) |
| #define | I2C_CR2_NACK ((uint32_t)0x00008000) |
| #define | I2C_CR2_NBYTES ((uint32_t)0x00FF0000) |
| #define | I2C_CR2_RELOAD ((uint32_t)0x01000000) |
| #define | I2C_CR2_AUTOEND ((uint32_t)0x02000000) |
| #define | I2C_CR2_PECBYTE ((uint32_t)0x04000000) |
| #define | I2C_OAR1_OA1 ((uint32_t)0x000003FF) |
| #define | I2C_OAR1_OA1MODE ((uint32_t)0x00000400) |
| #define | I2C_OAR1_OA1EN ((uint32_t)0x00008000) |
| #define | I2C_OAR2_OA2 ((uint32_t)0x000000FE) |
| #define | I2C_OAR2_OA2MSK ((uint32_t)0x00000700) |
| #define | I2C_OAR2_OA2EN ((uint32_t)0x00008000) |
| #define | I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) |
| #define | I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) |
| #define | I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) |
| #define | I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) |
| #define | I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) |
| #define | I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) |
| #define | I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) |
| #define | I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) |
| #define | I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) |
| #define | I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) |
| #define | I2C_ISR_TXE ((uint32_t)0x00000001) |
| #define | I2C_ISR_TXIS ((uint32_t)0x00000002) |
| #define | I2C_ISR_RXNE ((uint32_t)0x00000004) |
| #define | I2C_ISR_ADDR ((uint32_t)0x00000008) |
| #define | I2C_ISR_NACKF ((uint32_t)0x00000010) |
| #define | I2C_ISR_STOPF ((uint32_t)0x00000020) |
| #define | I2C_ISR_TC ((uint32_t)0x00000040) |
| #define | I2C_ISR_TCR ((uint32_t)0x00000080) |
| #define | I2C_ISR_BERR ((uint32_t)0x00000100) |
| #define | I2C_ISR_ARLO ((uint32_t)0x00000200) |
| #define | I2C_ISR_OVR ((uint32_t)0x00000400) |
| #define | I2C_ISR_PECERR ((uint32_t)0x00000800) |
| #define | I2C_ISR_TIMEOUT ((uint32_t)0x00001000) |
| #define | I2C_ISR_ALERT ((uint32_t)0x00002000) |
| #define | I2C_ISR_BUSY ((uint32_t)0x00008000) |
| #define | I2C_ISR_DIR ((uint32_t)0x00010000) |
| #define | I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) |
| #define | I2C_ICR_ADDRCF ((uint32_t)0x00000008) |
| #define | I2C_ICR_NACKCF ((uint32_t)0x00000010) |
| #define | I2C_ICR_STOPCF ((uint32_t)0x00000020) |
| #define | I2C_ICR_BERRCF ((uint32_t)0x00000100) |
| #define | I2C_ICR_ARLOCF ((uint32_t)0x00000200) |
| #define | I2C_ICR_OVRCF ((uint32_t)0x00000400) |
| #define | I2C_ICR_PECCF ((uint32_t)0x00000800) |
| #define | I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) |
| #define | I2C_ICR_ALERTCF ((uint32_t)0x00002000) |
| #define | I2C_PECR_PEC ((uint32_t)0x000000FF) |
| #define | I2C_RXDR_RXDATA ((uint32_t)0x000000FF) |
| #define | I2C_TXDR_TXDATA ((uint32_t)0x000000FF) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | IWDG_SR_WVU ((uint8_t)0x04) |
| #define | IWDG_WINR_WIN ((uint16_t)0x0FFF) |
| #define | PWR_CR_LPSDSR ((uint16_t)0x0001) |
| #define | PWR_CR_PDDS ((uint16_t)0x0002) |
| #define | PWR_CR_CWUF ((uint16_t)0x0004) |
| #define | PWR_CR_CSBF ((uint16_t)0x0008) |
| #define | PWR_CR_PVDE ((uint16_t)0x0010) |
| #define | PWR_CR_PLS ((uint16_t)0x00E0) |
| #define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV0 ((uint16_t)0x0000) |
| #define | PWR_CR_PLS_LEV1 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_LEV2 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_LEV3 ((uint16_t)0x0060) |
| #define | PWR_CR_PLS_LEV4 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) |
| #define | PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) |
| #define | PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) |
| #define | PWR_CR_DBP ((uint16_t)0x0100) |
| #define | PWR_CSR_WUF ((uint16_t)0x0001) |
| #define | PWR_CSR_SBF ((uint16_t)0x0002) |
| #define | PWR_CSR_PVDO ((uint16_t)0x0004) |
| #define | PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) |
| #define | PWR_CSR_EWUP1 ((uint16_t)0x0100) |
| #define | PWR_CSR_EWUP2 ((uint16_t)0x0200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) |
| #define | RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) |
| #define | RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) |
| #define | RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) |
| #define | RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) |
| #define | RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) |
| #define | RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) |
| #define | RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) |
| #define | RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) |
| #define | RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) |
| #define | RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) |
| #define | RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) |
| #define | RCC_AHBENR_TSEN ((uint32_t)0x01000000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_APB1ENR_CECEN ((uint32_t)0x40000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_LSEDRV ((uint32_t)0x00000018) |
| #define | RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) |
| #define | RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_OBL ((uint32_t)0x02000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) |
| #define | RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) |
| #define | RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) |
| #define | RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) |
| #define | RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) |
| #define | RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) |
| #define | RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) |
| #define | RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) |
| #define | RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) |
| #define | RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) |
| #define | RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) |
| #define | RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) |
| #define | RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) |
| #define | RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) |
| #define | RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) |
| #define | RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) |
| #define | RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR3_USART1SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) |
| #define | RCC_CFGR3_CECSW ((uint32_t)0x00000040) |
| #define | RCC_CFGR3_ADCSW ((uint32_t)0x00000100) |
| #define | RCC_CR2_HSI14ON ((uint32_t)0x00000001) |
| #define | RCC_CR2_HSI14RDY ((uint32_t)0x00000002) |
| #define | RCC_CR2_HSI14DIS ((uint32_t)0x00000004) |
| #define | RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_CALSEL ((uint32_t)0x00080000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_DCE ((uint32_t)0x00000080) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| #define | RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_SHPF ((uint32_t)0x00000008) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_SSR_SS ((uint32_t)0x0003FFFF) |
| #define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| #define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSSSR_SS ((uint32_t)0x0003FFFF) |
| #define | RTC_CAL_CALP ((uint32_t)0x00008000) |
| #define | RTC_CAL_CALW8 ((uint32_t)0x00004000) |
| #define | RTC_CAL_CALW16 ((uint32_t)0x00002000) |
| #define | RTC_CAL_CALM ((uint32_t)0x000001FF) |
| #define | RTC_CAL_CALM_0 ((uint32_t)0x00000001) |
| #define | RTC_CAL_CALM_1 ((uint32_t)0x00000002) |
| #define | RTC_CAL_CALM_2 ((uint32_t)0x00000004) |
| #define | RTC_CAL_CALM_3 ((uint32_t)0x00000008) |
| #define | RTC_CAL_CALM_4 ((uint32_t)0x00000010) |
| #define | RTC_CAL_CALM_5 ((uint32_t)0x00000020) |
| #define | RTC_CAL_CALM_6 ((uint32_t)0x00000040) |
| #define | RTC_CAL_CALM_7 ((uint32_t)0x00000080) |
| #define | RTC_CAL_CALM_8 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| #define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| #define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| #define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| #define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| #define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| #define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| #define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| #define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| #define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| #define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| #define | RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010) |
| #define | RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_CRCL ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint16_t)0x0001) |
| #define | SPI_CR2_TXDMAEN ((uint16_t)0x0002) |
| #define | SPI_CR2_SSOE ((uint16_t)0x0004) |
| #define | SPI_CR2_NSSP ((uint16_t)0x0008) |
| #define | SPI_CR2_FRF ((uint16_t)0x0010) |
| #define | SPI_CR2_ERRIE ((uint16_t)0x0020) |
| #define | SPI_CR2_RXNEIE ((uint16_t)0x0040) |
| #define | SPI_CR2_TXEIE ((uint16_t)0x0080) |
| #define | SPI_CR2_DS ((uint16_t)0x0F00) |
| #define | SPI_CR2_DS_0 ((uint16_t)0x0100) |
| #define | SPI_CR2_DS_1 ((uint16_t)0x0200) |
| #define | SPI_CR2_DS_2 ((uint16_t)0x0400) |
| #define | SPI_CR2_DS_3 ((uint16_t)0x0800) |
| #define | SPI_CR2_FRXTH ((uint16_t)0x1000) |
| #define | SPI_CR2_LDMARX ((uint16_t)0x2000) |
| #define | SPI_CR2_LDMATX ((uint16_t)0x4000) |
| #define | SPI_SR_RXNE ((uint16_t)0x0001) |
| #define | SPI_SR_TXE ((uint16_t)0x0002) |
| #define | SPI_SR_CHSIDE ((uint16_t)0x0004) |
| #define | SPI_SR_UDR ((uint16_t)0x0008) |
| #define | SPI_SR_CRCERR ((uint16_t)0x0010) |
| #define | SPI_SR_MODF ((uint16_t)0x0020) |
| #define | SPI_SR_OVR ((uint16_t)0x0040) |
| #define | SPI_SR_BSY ((uint16_t)0x0080) |
| #define | SPI_SR_FRE ((uint16_t)0x0100) |
| #define | SPI_SR_FRLVL ((uint16_t)0x0600) |
| #define | SPI_SR_FRLVL_0 ((uint16_t)0x0200) |
| #define | SPI_SR_FRLVL_1 ((uint16_t)0x0400) |
| #define | SPI_SR_FTLVL ((uint16_t)0x1800) |
| #define | SPI_SR_FTLVL_0 ((uint16_t)0x0800) |
| #define | SPI_SR_FTLVL_1 ((uint16_t)0x1000) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) |
| #define | SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) |
| #define | SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) |
| #define | SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) |
| #define | SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) |
| #define | SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) |
| #define | SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) |
| #define | SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) |
| #define | SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) |
| #define | SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCPC ((uint16_t)0x0001) |
| #define | TIM_CR2_CCUS ((uint16_t)0x0004) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
| #define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
| #define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
| #define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
| #define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
| #define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
| #define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_OCCS ((uint16_t)0x0008) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_COMIF ((uint16_t)0x0020) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_BIF ((uint16_t)0x0080) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_COMG ((uint8_t)0x20) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_EGR_BG ((uint8_t)0x80) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
| #define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
| #define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
| #define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
| #define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
| #define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
| #define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
| #define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
| #define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
| #define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
| #define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
| #define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
| #define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
| #define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
| #define | TIM_BDTR_BKE ((uint16_t)0x1000) |
| #define | TIM_BDTR_BKP ((uint16_t)0x2000) |
| #define | TIM_BDTR_AOE ((uint16_t)0x4000) |
| #define | TIM_BDTR_MOE ((uint16_t)0x8000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM14_OR_TI1_RMP ((uint16_t)0x0003) |
| #define | TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) |
| #define | TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) |
| #define | USART_CR1_UE ((uint32_t)0x00000001) |
| #define | USART_CR1_UESM ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_MME ((uint32_t)0x00002000) |
| #define | USART_CR1_CMIE ((uint32_t)0x00004000) |
| #define | USART_CR1_OVER8 ((uint32_t)0x00008000) |
| #define | USART_CR1_DEDT ((uint32_t)0x001F0000) |
| #define | USART_CR1_DEDT_0 ((uint32_t)0x00010000) |
| #define | USART_CR1_DEDT_1 ((uint32_t)0x00020000) |
| #define | USART_CR1_DEDT_2 ((uint32_t)0x00040000) |
| #define | USART_CR1_DEDT_3 ((uint32_t)0x00080000) |
| #define | USART_CR1_DEDT_4 ((uint32_t)0x00100000) |
| #define | USART_CR1_DEAT ((uint32_t)0x03E00000) |
| #define | USART_CR1_DEAT_0 ((uint32_t)0x00200000) |
| #define | USART_CR1_DEAT_1 ((uint32_t)0x00400000) |
| #define | USART_CR1_DEAT_2 ((uint32_t)0x00800000) |
| #define | USART_CR1_DEAT_3 ((uint32_t)0x01000000) |
| #define | USART_CR1_DEAT_4 ((uint32_t)0x02000000) |
| #define | USART_CR1_RTOIE ((uint32_t)0x04000000) |
| #define | USART_CR1_EOBIE ((uint32_t)0x08000000) |
| #define | USART_CR2_ADDM7 ((uint32_t)0x00000010) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR2_SWAP ((uint32_t)0x00008000) |
| #define | USART_CR2_RXINV ((uint32_t)0x00010000) |
| #define | USART_CR2_TXINV ((uint32_t)0x00020000) |
| #define | USART_CR2_DATAINV ((uint32_t)0x00040000) |
| #define | USART_CR2_MSBFIRST ((uint32_t)0x00080000) |
| #define | USART_CR2_ABREN ((uint32_t)0x00100000) |
| #define | USART_CR2_ABRMODE ((uint32_t)0x00600000) |
| #define | USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) |
| #define | USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) |
| #define | USART_CR2_RTOEN ((uint32_t)0x00800000) |
| #define | USART_CR2_ADD ((uint32_t)0xFF000000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_CR3_ONEBIT ((uint32_t)0x00000800) |
| #define | USART_CR3_OVRDIS ((uint32_t)0x00001000) |
| #define | USART_CR3_DDRE ((uint32_t)0x00002000) |
| #define | USART_CR3_DEM ((uint32_t)0x00004000) |
| #define | USART_CR3_DEP ((uint32_t)0x00008000) |
| #define | USART_CR3_SCARCNT ((uint32_t)0x000E0000) |
| #define | USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) |
| #define | USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) |
| #define | USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) |
| #define | USART_CR3_WUS ((uint32_t)0x00300000) |
| #define | USART_CR3_WUS_0 ((uint32_t)0x00100000) |
| #define | USART_CR3_WUS_1 ((uint32_t)0x00200000) |
| #define | USART_CR3_WUFIE ((uint32_t)0x00400000) |
| #define | USART_BRR_DIV_FRACTION ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | USART_RTOR_RTO ((uint32_t)0x00FFFFFF) |
| #define | USART_RTOR_BLEN ((uint32_t)0xFF000000) |
| #define | USART_RQR_ABRRQ ((uint16_t)0x0001) |
| #define | USART_RQR_SBKRQ ((uint16_t)0x0002) |
| #define | USART_RQR_MMRQ ((uint16_t)0x0004) |
| #define | USART_RQR_RXFRQ ((uint16_t)0x0008) |
| #define | USART_RQR_TXFRQ ((uint16_t)0x0010) |
| #define | USART_ISR_PE ((uint32_t)0x00000001) |
| #define | USART_ISR_FE ((uint32_t)0x00000002) |
| #define | USART_ISR_NE ((uint32_t)0x00000004) |
| #define | USART_ISR_ORE ((uint32_t)0x00000008) |
| #define | USART_ISR_IDLE ((uint32_t)0x00000010) |
| #define | USART_ISR_RXNE ((uint32_t)0x00000020) |
| #define | USART_ISR_TC ((uint32_t)0x00000040) |
| #define | USART_ISR_TXE ((uint32_t)0x00000080) |
| #define | USART_ISR_LBD ((uint32_t)0x00000100) |
| #define | USART_ISR_CTSIF ((uint32_t)0x00000200) |
| #define | USART_ISR_CTS ((uint32_t)0x00000400) |
| #define | USART_ISR_RTOF ((uint32_t)0x00000800) |
| #define | USART_ISR_EOBF ((uint32_t)0x00001000) |
| #define | USART_ISR_ABRE ((uint32_t)0x00004000) |
| #define | USART_ISR_ABRF ((uint32_t)0x00008000) |
| #define | USART_ISR_BUSY ((uint32_t)0x00010000) |
| #define | USART_ISR_CMF ((uint32_t)0x00020000) |
| #define | USART_ISR_SBKF ((uint32_t)0x00040000) |
| #define | USART_ISR_RWU ((uint32_t)0x00080000) |
| #define | USART_ISR_WUF ((uint32_t)0x00100000) |
| #define | USART_ISR_TEACK ((uint32_t)0x00200000) |
| #define | USART_ISR_REACK ((uint32_t)0x00400000) |
| #define | USART_ICR_PECF ((uint32_t)0x00000001) |
| #define | USART_ICR_FECF ((uint32_t)0x00000002) |
| #define | USART_ICR_NCF ((uint32_t)0x00000004) |
| #define | USART_ICR_ORECF ((uint32_t)0x00000008) |
| #define | USART_ICR_IDLECF ((uint32_t)0x00000010) |
| #define | USART_ICR_TCCF ((uint32_t)0x00000040) |
| #define | USART_ICR_LBDCF ((uint32_t)0x00000100) |
| #define | USART_ICR_CTSCF ((uint32_t)0x00000200) |
| #define | USART_ICR_RTOCF ((uint32_t)0x00000800) |
| #define | USART_ICR_EOBCF ((uint32_t)0x00001000) |
| #define | USART_ICR_CMCF ((uint32_t)0x00020000) |
| #define | USART_ICR_WUCF ((uint32_t)0x00100000) |
| #define | USART_RDR_RDR ((uint16_t)0x01FF) |
| #define | USART_TDR_TDR ((uint16_t)0x01FF) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint8_t)0x01) |
| #define | PWR_CR_LPDS ((uint16_t)0x0001) |
| #define | PWR_CR_PDDS ((uint16_t)0x0002) |
| #define | PWR_CR_CWUF ((uint16_t)0x0004) |
| #define | PWR_CR_CSBF ((uint16_t)0x0008) |
| #define | PWR_CR_PVDE ((uint16_t)0x0010) |
| #define | PWR_CR_PLS ((uint16_t)0x00E0) |
| #define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_2V2 ((uint16_t)0x0000) |
| #define | PWR_CR_PLS_2V3 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_2V4 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2V5 ((uint16_t)0x0060) |
| #define | PWR_CR_PLS_2V6 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_2V7 ((uint16_t)0x00A0) |
| #define | PWR_CR_PLS_2V8 ((uint16_t)0x00C0) |
| #define | PWR_CR_PLS_2V9 ((uint16_t)0x00E0) |
| #define | PWR_CR_DBP ((uint16_t)0x0100) |
| #define | PWR_CSR_WUF ((uint16_t)0x0001) |
| #define | PWR_CSR_SBF ((uint16_t)0x0002) |
| #define | PWR_CSR_PVDO ((uint16_t)0x0004) |
| #define | PWR_CSR_EWUP ((uint16_t)0x0100) |
| #define | BKP_DR1_D ((uint16_t)0xFFFF) |
| #define | BKP_DR2_D ((uint16_t)0xFFFF) |
| #define | BKP_DR3_D ((uint16_t)0xFFFF) |
| #define | BKP_DR4_D ((uint16_t)0xFFFF) |
| #define | BKP_DR5_D ((uint16_t)0xFFFF) |
| #define | BKP_DR6_D ((uint16_t)0xFFFF) |
| #define | BKP_DR7_D ((uint16_t)0xFFFF) |
| #define | BKP_DR8_D ((uint16_t)0xFFFF) |
| #define | BKP_DR9_D ((uint16_t)0xFFFF) |
| #define | BKP_DR10_D ((uint16_t)0xFFFF) |
| #define | BKP_DR11_D ((uint16_t)0xFFFF) |
| #define | BKP_DR12_D ((uint16_t)0xFFFF) |
| #define | BKP_DR13_D ((uint16_t)0xFFFF) |
| #define | BKP_DR14_D ((uint16_t)0xFFFF) |
| #define | BKP_DR15_D ((uint16_t)0xFFFF) |
| #define | BKP_DR16_D ((uint16_t)0xFFFF) |
| #define | BKP_DR17_D ((uint16_t)0xFFFF) |
| #define | BKP_DR18_D ((uint16_t)0xFFFF) |
| #define | BKP_DR19_D ((uint16_t)0xFFFF) |
| #define | BKP_DR20_D ((uint16_t)0xFFFF) |
| #define | BKP_DR21_D ((uint16_t)0xFFFF) |
| #define | BKP_DR22_D ((uint16_t)0xFFFF) |
| #define | BKP_DR23_D ((uint16_t)0xFFFF) |
| #define | BKP_DR24_D ((uint16_t)0xFFFF) |
| #define | BKP_DR25_D ((uint16_t)0xFFFF) |
| #define | BKP_DR26_D ((uint16_t)0xFFFF) |
| #define | BKP_DR27_D ((uint16_t)0xFFFF) |
| #define | BKP_DR28_D ((uint16_t)0xFFFF) |
| #define | BKP_DR29_D ((uint16_t)0xFFFF) |
| #define | BKP_DR30_D ((uint16_t)0xFFFF) |
| #define | BKP_DR31_D ((uint16_t)0xFFFF) |
| #define | BKP_DR32_D ((uint16_t)0xFFFF) |
| #define | BKP_DR33_D ((uint16_t)0xFFFF) |
| #define | BKP_DR34_D ((uint16_t)0xFFFF) |
| #define | BKP_DR35_D ((uint16_t)0xFFFF) |
| #define | BKP_DR36_D ((uint16_t)0xFFFF) |
| #define | BKP_DR37_D ((uint16_t)0xFFFF) |
| #define | BKP_DR38_D ((uint16_t)0xFFFF) |
| #define | BKP_DR39_D ((uint16_t)0xFFFF) |
| #define | BKP_DR40_D ((uint16_t)0xFFFF) |
| #define | BKP_DR41_D ((uint16_t)0xFFFF) |
| #define | BKP_DR42_D ((uint16_t)0xFFFF) |
| #define | BKP_RTCCR_CAL ((uint16_t)0x007F) |
| #define | BKP_RTCCR_CCO ((uint16_t)0x0080) |
| #define | BKP_RTCCR_ASOE ((uint16_t)0x0100) |
| #define | BKP_RTCCR_ASOS ((uint16_t)0x0200) |
| #define | BKP_CR_TPE ((uint8_t)0x01) |
| #define | BKP_CR_TPAL ((uint8_t)0x02) |
| #define | BKP_CSR_CTE ((uint16_t)0x0001) |
| #define | BKP_CSR_CTI ((uint16_t)0x0002) |
| #define | BKP_CSR_TPIE ((uint16_t)0x0004) |
| #define | BKP_CSR_TEF ((uint16_t)0x0100) |
| #define | BKP_CSR_TIF ((uint16_t)0x0200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_AHBENR_DMA1EN ((uint16_t)0x0001) |
| #define | RCC_AHBENR_SRAMEN ((uint16_t)0x0004) |
| #define | RCC_AHBENR_FLITFEN ((uint16_t)0x0010) |
| #define | RCC_AHBENR_CRCEN ((uint16_t)0x0040) |
| #define | RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | GPIO_CRL_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRL_MODE0 ((uint32_t)0x00000003) |
| #define | GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRL_MODE1 ((uint32_t)0x00000030) |
| #define | GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRL_MODE2 ((uint32_t)0x00000300) |
| #define | GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRL_MODE3 ((uint32_t)0x00003000) |
| #define | GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRL_MODE4 ((uint32_t)0x00030000) |
| #define | GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRL_MODE5 ((uint32_t)0x00300000) |
| #define | GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRL_MODE6 ((uint32_t)0x03000000) |
| #define | GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRL_MODE7 ((uint32_t)0x30000000) |
| #define | GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRL_CNF0 ((uint32_t)0x0000000C) |
| #define | GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRL_CNF1 ((uint32_t)0x000000C0) |
| #define | GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRL_CNF2 ((uint32_t)0x00000C00) |
| #define | GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRL_CNF3 ((uint32_t)0x0000C000) |
| #define | GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRL_CNF4 ((uint32_t)0x000C0000) |
| #define | GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRL_CNF5 ((uint32_t)0x00C00000) |
| #define | GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRL_CNF6 ((uint32_t)0x0C000000) |
| #define | GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRL_CNF7 ((uint32_t)0xC0000000) |
| #define | GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) |
| #define | GPIO_CRH_MODE ((uint32_t)0x33333333) |
| #define | GPIO_CRH_MODE8 ((uint32_t)0x00000003) |
| #define | GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) |
| #define | GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) |
| #define | GPIO_CRH_MODE9 ((uint32_t)0x00000030) |
| #define | GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) |
| #define | GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) |
| #define | GPIO_CRH_MODE10 ((uint32_t)0x00000300) |
| #define | GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) |
| #define | GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) |
| #define | GPIO_CRH_MODE11 ((uint32_t)0x00003000) |
| #define | GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) |
| #define | GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) |
| #define | GPIO_CRH_MODE12 ((uint32_t)0x00030000) |
| #define | GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) |
| #define | GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) |
| #define | GPIO_CRH_MODE13 ((uint32_t)0x00300000) |
| #define | GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) |
| #define | GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) |
| #define | GPIO_CRH_MODE14 ((uint32_t)0x03000000) |
| #define | GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) |
| #define | GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) |
| #define | GPIO_CRH_MODE15 ((uint32_t)0x30000000) |
| #define | GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) |
| #define | GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) |
| #define | GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) |
| #define | GPIO_CRH_CNF8 ((uint32_t)0x0000000C) |
| #define | GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) |
| #define | GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) |
| #define | GPIO_CRH_CNF9 ((uint32_t)0x000000C0) |
| #define | GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) |
| #define | GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) |
| #define | GPIO_CRH_CNF10 ((uint32_t)0x00000C00) |
| #define | GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) |
| #define | GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) |
| #define | GPIO_CRH_CNF11 ((uint32_t)0x0000C000) |
| #define | GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) |
| #define | GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) |
| #define | GPIO_CRH_CNF12 ((uint32_t)0x000C0000) |
| #define | GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) |
| #define | GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) |
| #define | GPIO_CRH_CNF13 ((uint32_t)0x00C00000) |
| #define | GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) |
| #define | GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) |
| #define | GPIO_CRH_CNF14 ((uint32_t)0x0C000000) |
| #define | GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) |
| #define | GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) |
| #define | GPIO_CRH_CNF15 ((uint32_t)0xC0000000) |
| #define | GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) |
| #define | GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR0 ((uint16_t)0x0001) |
| #define | GPIO_IDR_IDR1 ((uint16_t)0x0002) |
| #define | GPIO_IDR_IDR2 ((uint16_t)0x0004) |
| #define | GPIO_IDR_IDR3 ((uint16_t)0x0008) |
| #define | GPIO_IDR_IDR4 ((uint16_t)0x0010) |
| #define | GPIO_IDR_IDR5 ((uint16_t)0x0020) |
| #define | GPIO_IDR_IDR6 ((uint16_t)0x0040) |
| #define | GPIO_IDR_IDR7 ((uint16_t)0x0080) |
| #define | GPIO_IDR_IDR8 ((uint16_t)0x0100) |
| #define | GPIO_IDR_IDR9 ((uint16_t)0x0200) |
| #define | GPIO_IDR_IDR10 ((uint16_t)0x0400) |
| #define | GPIO_IDR_IDR11 ((uint16_t)0x0800) |
| #define | GPIO_IDR_IDR12 ((uint16_t)0x1000) |
| #define | GPIO_IDR_IDR13 ((uint16_t)0x2000) |
| #define | GPIO_IDR_IDR14 ((uint16_t)0x4000) |
| #define | GPIO_IDR_IDR15 ((uint16_t)0x8000) |
| #define | GPIO_ODR_ODR0 ((uint16_t)0x0001) |
| #define | GPIO_ODR_ODR1 ((uint16_t)0x0002) |
| #define | GPIO_ODR_ODR2 ((uint16_t)0x0004) |
| #define | GPIO_ODR_ODR3 ((uint16_t)0x0008) |
| #define | GPIO_ODR_ODR4 ((uint16_t)0x0010) |
| #define | GPIO_ODR_ODR5 ((uint16_t)0x0020) |
| #define | GPIO_ODR_ODR6 ((uint16_t)0x0040) |
| #define | GPIO_ODR_ODR7 ((uint16_t)0x0080) |
| #define | GPIO_ODR_ODR8 ((uint16_t)0x0100) |
| #define | GPIO_ODR_ODR9 ((uint16_t)0x0200) |
| #define | GPIO_ODR_ODR10 ((uint16_t)0x0400) |
| #define | GPIO_ODR_ODR11 ((uint16_t)0x0800) |
| #define | GPIO_ODR_ODR12 ((uint16_t)0x1000) |
| #define | GPIO_ODR_ODR13 ((uint16_t)0x2000) |
| #define | GPIO_ODR_ODR14 ((uint16_t)0x4000) |
| #define | GPIO_ODR_ODR15 ((uint16_t)0x8000) |
| #define | GPIO_BSRR_BS0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR15 ((uint32_t)0x80000000) |
| #define | GPIO_BRR_BR0 ((uint16_t)0x0001) |
| #define | GPIO_BRR_BR1 ((uint16_t)0x0002) |
| #define | GPIO_BRR_BR2 ((uint16_t)0x0004) |
| #define | GPIO_BRR_BR3 ((uint16_t)0x0008) |
| #define | GPIO_BRR_BR4 ((uint16_t)0x0010) |
| #define | GPIO_BRR_BR5 ((uint16_t)0x0020) |
| #define | GPIO_BRR_BR6 ((uint16_t)0x0040) |
| #define | GPIO_BRR_BR7 ((uint16_t)0x0080) |
| #define | GPIO_BRR_BR8 ((uint16_t)0x0100) |
| #define | GPIO_BRR_BR9 ((uint16_t)0x0200) |
| #define | GPIO_BRR_BR10 ((uint16_t)0x0400) |
| #define | GPIO_BRR_BR11 ((uint16_t)0x0800) |
| #define | GPIO_BRR_BR12 ((uint16_t)0x1000) |
| #define | GPIO_BRR_BR13 ((uint16_t)0x2000) |
| #define | GPIO_BRR_BR14 ((uint16_t)0x4000) |
| #define | GPIO_BRR_BR15 ((uint16_t)0x8000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | AFIO_EVCR_PIN ((uint8_t)0x0F) |
| #define | AFIO_EVCR_PIN_0 ((uint8_t)0x01) |
| #define | AFIO_EVCR_PIN_1 ((uint8_t)0x02) |
| #define | AFIO_EVCR_PIN_2 ((uint8_t)0x04) |
| #define | AFIO_EVCR_PIN_3 ((uint8_t)0x08) |
| #define | AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) |
| #define | AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) |
| #define | AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) |
| #define | AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) |
| #define | AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) |
| #define | AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) |
| #define | AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) |
| #define | AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) |
| #define | AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) |
| #define | AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) |
| #define | AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) |
| #define | AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) |
| #define | AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) |
| #define | AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) |
| #define | AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) |
| #define | AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) |
| #define | AFIO_EVCR_PORT ((uint8_t)0x70) |
| #define | AFIO_EVCR_PORT_0 ((uint8_t)0x10) |
| #define | AFIO_EVCR_PORT_1 ((uint8_t)0x20) |
| #define | AFIO_EVCR_PORT_2 ((uint8_t)0x40) |
| #define | AFIO_EVCR_PORT_PA ((uint8_t)0x00) |
| #define | AFIO_EVCR_PORT_PB ((uint8_t)0x10) |
| #define | AFIO_EVCR_PORT_PC ((uint8_t)0x20) |
| #define | AFIO_EVCR_PORT_PD ((uint8_t)0x30) |
| #define | AFIO_EVCR_PORT_PE ((uint8_t)0x40) |
| #define | AFIO_EVCR_EVOE ((uint8_t)0x80) |
| #define | AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) |
| #define | AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) |
| #define | AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) |
| #define | AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) |
| #define | AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) |
| #define | AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) |
| #define | AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) |
| #define | AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) |
| #define | AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) |
| #define | AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) |
| #define | AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) |
| #define | AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) |
| #define | AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) |
| #define | AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) |
| #define | AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) |
| #define | AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) |
| #define | AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) |
| #define | AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) |
| #define | AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) |
| #define | AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) |
| #define | AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) |
| #define | AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) |
| #define | AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) |
| #define | AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) |
| #define | AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) |
| #define | AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) |
| #define | AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) |
| #define | AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) |
| #define | AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) |
| #define | AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) |
| #define | AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) |
| #define | AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) |
| #define | AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
| #define | AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
| #define | AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
| #define | AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
| #define | AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
| #define | AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
| #define | AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
| #define | AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
| #define | AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
| #define | AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
| #define | AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
| #define | AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
| #define | AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
| #define | AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
| #define | AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
| #define | AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
| #define | AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
| #define | AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
| #define | AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
| #define | AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
| #define | AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
| #define | AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
| #define | AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
| #define | AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
| #define | AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
| #define | AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
| #define | AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
| #define | AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
| #define | AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
| #define | AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
| #define | AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
| #define | AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
| #define | AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
| #define | AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
| #define | AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
| #define | AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
| #define | AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
| #define | AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
| #define | AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| #define | AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
| #define | AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) |
| #define | SCB_SCR_SLEEPDEEP ((uint8_t)0x04) |
| #define | SCB_SCR_SEVONPEND ((uint8_t)0x10) |
| #define | SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) |
| #define | SCB_CCR_USERSETMPEND ((uint16_t)0x0002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) |
| #define | SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) |
| #define | SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) |
| #define | SCB_CCR_STKALIGN ((uint16_t)0x0200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint8_t)0x01) |
| #define | SCB_DFSR_BKPT ((uint8_t)0x02) |
| #define | SCB_DFSR_DWTTRAP ((uint8_t)0x04) |
| #define | SCB_DFSR_VCATCH ((uint8_t)0x08) |
| #define | SCB_DFSR_EXTERNAL ((uint8_t)0x10) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR1_EN ((uint16_t)0x0001) |
| #define | DMA_CCR1_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR1_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR1_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR1_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR1_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR1_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR1_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR1_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR1_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR1_PL ((uint16_t)0x3000) |
| #define | DMA_CCR1_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR1_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR1_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR2_EN ((uint16_t)0x0001) |
| #define | DMA_CCR2_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR2_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR2_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR2_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR2_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR2_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR2_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR2_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR2_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR2_PL ((uint16_t)0x3000) |
| #define | DMA_CCR2_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR2_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR2_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR3_EN ((uint16_t)0x0001) |
| #define | DMA_CCR3_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR3_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR3_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR3_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR3_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR3_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR3_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR3_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR3_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR3_PL ((uint16_t)0x3000) |
| #define | DMA_CCR3_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR3_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR3_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR4_EN ((uint16_t)0x0001) |
| #define | DMA_CCR4_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR4_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR4_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR4_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR4_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR4_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR4_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR4_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR4_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR4_PL ((uint16_t)0x3000) |
| #define | DMA_CCR4_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR4_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR4_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR5_EN ((uint16_t)0x0001) |
| #define | DMA_CCR5_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR5_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR5_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR5_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR5_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR5_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR5_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR5_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR5_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR5_PL ((uint16_t)0x3000) |
| #define | DMA_CCR5_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR5_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR5_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR6_EN ((uint16_t)0x0001) |
| #define | DMA_CCR6_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR6_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR6_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR6_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR6_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR6_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR6_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR6_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR6_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR6_PL ((uint16_t)0x3000) |
| #define | DMA_CCR6_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR6_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR6_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR7_EN ((uint16_t)0x0001) |
| #define | DMA_CCR7_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR7_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR7_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR7_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR7_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR7_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR7_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR7_PSIZE , ((uint16_t)0x0300) |
| #define | DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR7_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR7_PL ((uint16_t)0x3000) |
| #define | DMA_CCR7_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR7_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR7_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CNDTR1_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR2_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR3_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR4_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR5_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR6_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR7_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) |
| #define | ADC_SR_AWD ((uint8_t)0x01) |
| #define | ADC_SR_EOC ((uint8_t)0x02) |
| #define | ADC_SR_JEOC ((uint8_t)0x04) |
| #define | ADC_SR_JSTRT ((uint8_t)0x08) |
| #define | ADC_SR_STRT ((uint8_t)0x10) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_DUALMOD ((uint32_t)0x000F0000) |
| #define | ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) |
| #define | ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) |
| #define | ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) |
| #define | ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
| #define | ADC_HTR_HT ((uint16_t)0x0FFF) |
| #define | ADC_LTR_LT ((uint16_t)0x0FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | CEC_CFGR_PE ((uint16_t)0x0001) |
| #define | CEC_CFGR_IE ((uint16_t)0x0002) |
| #define | CEC_CFGR_BTEM ((uint16_t)0x0004) |
| #define | CEC_CFGR_BPEM ((uint16_t)0x0008) |
| #define | CEC_OAR_OA ((uint16_t)0x000F) |
| #define | CEC_OAR_OA_0 ((uint16_t)0x0001) |
| #define | CEC_OAR_OA_1 ((uint16_t)0x0002) |
| #define | CEC_OAR_OA_2 ((uint16_t)0x0004) |
| #define | CEC_OAR_OA_3 ((uint16_t)0x0008) |
| #define | CEC_PRES_PRES ((uint16_t)0x3FFF) |
| #define | CEC_ESR_BTE ((uint16_t)0x0001) |
| #define | CEC_ESR_BPE ((uint16_t)0x0002) |
| #define | CEC_ESR_RBTFE ((uint16_t)0x0004) |
| #define | CEC_ESR_SBE ((uint16_t)0x0008) |
| #define | CEC_ESR_ACKE ((uint16_t)0x0010) |
| #define | CEC_ESR_LINE ((uint16_t)0x0020) |
| #define | CEC_ESR_TBTFE ((uint16_t)0x0040) |
| #define | CEC_CSR_TSOM ((uint16_t)0x0001) |
| #define | CEC_CSR_TEOM ((uint16_t)0x0002) |
| #define | CEC_CSR_TERR ((uint16_t)0x0004) |
| #define | CEC_CSR_TBTRF ((uint16_t)0x0008) |
| #define | CEC_CSR_RSOM ((uint16_t)0x0010) |
| #define | CEC_CSR_REOM ((uint16_t)0x0020) |
| #define | CEC_CSR_RERR ((uint16_t)0x0040) |
| #define | CEC_CSR_RBTF ((uint16_t)0x0080) |
| #define | CEC_TXD_TXD ((uint16_t)0x00FF) |
| #define | CEC_RXD_RXD ((uint16_t)0x00FF) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCPC ((uint16_t)0x0001) |
| #define | TIM_CR2_CCUS ((uint16_t)0x0004) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
| #define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
| #define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
| #define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
| #define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
| #define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
| #define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_COMIF ((uint16_t)0x0020) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_BIF ((uint16_t)0x0080) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_COMG ((uint8_t)0x20) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_EGR_BG ((uint8_t)0x80) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
| #define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
| #define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
| #define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
| #define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
| #define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
| #define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
| #define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
| #define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
| #define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
| #define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
| #define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
| #define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
| #define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
| #define | TIM_BDTR_BKE ((uint16_t)0x1000) |
| #define | TIM_BDTR_BKP ((uint16_t)0x2000) |
| #define | TIM_BDTR_AOE ((uint16_t)0x4000) |
| #define | TIM_BDTR_MOE ((uint16_t)0x8000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | RTC_CRH_SECIE ((uint8_t)0x01) |
| #define | RTC_CRH_ALRIE ((uint8_t)0x02) |
| #define | RTC_CRH_OWIE ((uint8_t)0x04) |
| #define | RTC_CRL_SECF ((uint8_t)0x01) |
| #define | RTC_CRL_ALRF ((uint8_t)0x02) |
| #define | RTC_CRL_OWF ((uint8_t)0x04) |
| #define | RTC_CRL_RSF ((uint8_t)0x08) |
| #define | RTC_CRL_CNF ((uint8_t)0x10) |
| #define | RTC_CRL_RTOFF ((uint8_t)0x20) |
| #define | RTC_PRLH_PRL ((uint16_t)0x000F) |
| #define | RTC_PRLL_PRL ((uint16_t)0xFFFF) |
| #define | RTC_DIVH_RTC_DIV ((uint16_t)0x000F) |
| #define | RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) |
| #define | RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) |
| #define | RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) |
| #define | RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) |
| #define | RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | FSMC_BCR1_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR1_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR1_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR1_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR1_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR1_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR1_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR2_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR2_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR2_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR2_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR2_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR2_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR2_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR3_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR3_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR3_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR3_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR3_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR3_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR3_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR4_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR4_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR4_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR4_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR4_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR4_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR4_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR2_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR2_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR2_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR2_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR2_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR2_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR3_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR3_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR3_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR3_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR3_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR3_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR4_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR4_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR4_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR4_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR4_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR4_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_SR2_IRS ((uint8_t)0x01) |
| #define | FSMC_SR2_ILS ((uint8_t)0x02) |
| #define | FSMC_SR2_IFS ((uint8_t)0x04) |
| #define | FSMC_SR2_IREN ((uint8_t)0x08) |
| #define | FSMC_SR2_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR2_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR2_FEMPT ((uint8_t)0x40) |
| #define | FSMC_SR3_IRS ((uint8_t)0x01) |
| #define | FSMC_SR3_ILS ((uint8_t)0x02) |
| #define | FSMC_SR3_IFS ((uint8_t)0x04) |
| #define | FSMC_SR3_IREN ((uint8_t)0x08) |
| #define | FSMC_SR3_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR3_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR3_FEMPT ((uint8_t)0x40) |
| #define | FSMC_SR4_IRS ((uint8_t)0x01) |
| #define | FSMC_SR4_ILS ((uint8_t)0x02) |
| #define | FSMC_SR4_IFS ((uint8_t)0x04) |
| #define | FSMC_SR4_IREN ((uint8_t)0x08) |
| #define | FSMC_SR4_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR4_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR4_FEMPT ((uint8_t)0x40) |
| #define | FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) |
| #define | FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) |
| #define | FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint16_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint16_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | USB_EP0R_EA ((uint16_t)0x000F) |
| #define | USB_EP0R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP0R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP0R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP0R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP0R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP0R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP0R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP0R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP0R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP1R_EA ((uint16_t)0x000F) |
| #define | USB_EP1R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP1R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP1R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP1R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP1R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP1R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP1R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP1R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP1R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP2R_EA ((uint16_t)0x000F) |
| #define | USB_EP2R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP2R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP2R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP2R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP2R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP2R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP2R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP2R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP2R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP3R_EA ((uint16_t)0x000F) |
| #define | USB_EP3R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP3R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP3R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP3R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP3R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP3R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP3R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP3R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP3R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP4R_EA ((uint16_t)0x000F) |
| #define | USB_EP4R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP4R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP4R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP4R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP4R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP4R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP4R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP4R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP4R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP5R_EA ((uint16_t)0x000F) |
| #define | USB_EP5R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP5R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP5R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP5R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP5R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP5R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP5R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP5R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP5R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP6R_EA ((uint16_t)0x000F) |
| #define | USB_EP6R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP6R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP6R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP6R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP6R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP6R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP6R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP6R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP6R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP7R_EA ((uint16_t)0x000F) |
| #define | USB_EP7R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP7R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP7R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP7R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP7R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP7R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP7R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP7R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP7R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_CNTR_FRES ((uint16_t)0x0001) |
| #define | USB_CNTR_PDWN ((uint16_t)0x0002) |
| #define | USB_CNTR_LP_MODE ((uint16_t)0x0004) |
| #define | USB_CNTR_FSUSP ((uint16_t)0x0008) |
| #define | USB_CNTR_RESUME ((uint16_t)0x0010) |
| #define | USB_CNTR_ESOFM ((uint16_t)0x0100) |
| #define | USB_CNTR_SOFM ((uint16_t)0x0200) |
| #define | USB_CNTR_RESETM ((uint16_t)0x0400) |
| #define | USB_CNTR_SUSPM ((uint16_t)0x0800) |
| #define | USB_CNTR_WKUPM ((uint16_t)0x1000) |
| #define | USB_CNTR_ERRM ((uint16_t)0x2000) |
| #define | USB_CNTR_PMAOVRM ((uint16_t)0x4000) |
| #define | USB_CNTR_CTRM ((uint16_t)0x8000) |
| #define | USB_ISTR_EP_ID ((uint16_t)0x000F) |
| #define | USB_ISTR_DIR ((uint16_t)0x0010) |
| #define | USB_ISTR_ESOF ((uint16_t)0x0100) |
| #define | USB_ISTR_SOF ((uint16_t)0x0200) |
| #define | USB_ISTR_RESET ((uint16_t)0x0400) |
| #define | USB_ISTR_SUSP ((uint16_t)0x0800) |
| #define | USB_ISTR_WKUP ((uint16_t)0x1000) |
| #define | USB_ISTR_ERR ((uint16_t)0x2000) |
| #define | USB_ISTR_PMAOVR ((uint16_t)0x4000) |
| #define | USB_ISTR_CTR ((uint16_t)0x8000) |
| #define | USB_FNR_FN ((uint16_t)0x07FF) |
| #define | USB_FNR_LSOF ((uint16_t)0x1800) |
| #define | USB_FNR_LCK ((uint16_t)0x2000) |
| #define | USB_FNR_RXDM ((uint16_t)0x4000) |
| #define | USB_FNR_RXDP ((uint16_t)0x8000) |
| #define | USB_DADDR_ADD ((uint8_t)0x7F) |
| #define | USB_DADDR_ADD0 ((uint8_t)0x01) |
| #define | USB_DADDR_ADD1 ((uint8_t)0x02) |
| #define | USB_DADDR_ADD2 ((uint8_t)0x04) |
| #define | USB_DADDR_ADD3 ((uint8_t)0x08) |
| #define | USB_DADDR_ADD4 ((uint8_t)0x10) |
| #define | USB_DADDR_ADD5 ((uint8_t)0x20) |
| #define | USB_DADDR_ADD6 ((uint8_t)0x40) |
| #define | USB_DADDR_EF ((uint8_t)0x80) |
| #define | USB_BTABLE_BTABLE ((uint16_t)0xFFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | CAN_MCR_INRQ ((uint16_t)0x0001) |
| #define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
| #define | CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define | CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define | CAN_MCR_NART ((uint16_t)0x0010) |
| #define | CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define | CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define | CAN_MCR_TTCM ((uint16_t)0x0080) |
| #define | CAN_MCR_RESET ((uint16_t)0x8000) |
| #define | CAN_MSR_INAK ((uint16_t)0x0001) |
| #define | CAN_MSR_SLAK ((uint16_t)0x0002) |
| #define | CAN_MSR_ERRI ((uint16_t)0x0004) |
| #define | CAN_MSR_WKUI ((uint16_t)0x0008) |
| #define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
| #define | CAN_MSR_TXM ((uint16_t)0x0100) |
| #define | CAN_MSR_RXM ((uint16_t)0x0200) |
| #define | CAN_MSR_SAMP ((uint16_t)0x0400) |
| #define | CAN_MSR_RX ((uint16_t)0x0800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
| #define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
| #define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
| #define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
| #define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
| #define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
| #define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
| #define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint8_t)0x01) |
| #define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
| #define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
| #define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
| #define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
| #define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
| #define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
| #define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
| #define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
| #define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
| #define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
| #define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
| #define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
| #define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
| #define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
| #define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
| #define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
| #define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
| #define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
| #define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
| #define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
| #define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
| #define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
| #define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
| #define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
| #define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
| #define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
| #define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
| #define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
| #define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
| #define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
| #define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
| #define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
| #define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
| #define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
| #define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
| #define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
| #define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
| #define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
| #define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
| #define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
| #define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
| #define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
| #define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
| #define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
| #define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
| #define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
| #define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
| #define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
| #define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
| #define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
| #define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
| #define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
| #define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
| #define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
| #define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
| #define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
| #define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
| #define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
| #define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
| #define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_DFF ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint8_t)0x01) |
| #define | SPI_CR2_TXDMAEN ((uint8_t)0x02) |
| #define | SPI_CR2_SSOE ((uint8_t)0x04) |
| #define | SPI_CR2_ERRIE ((uint8_t)0x20) |
| #define | SPI_CR2_RXNEIE ((uint8_t)0x40) |
| #define | SPI_CR2_TXEIE ((uint8_t)0x80) |
| #define | SPI_SR_RXNE ((uint8_t)0x01) |
| #define | SPI_SR_TXE ((uint8_t)0x02) |
| #define | SPI_SR_CHSIDE ((uint8_t)0x04) |
| #define | SPI_SR_UDR ((uint8_t)0x08) |
| #define | SPI_SR_CRCERR ((uint8_t)0x10) |
| #define | SPI_SR_MODF ((uint8_t)0x20) |
| #define | SPI_SR_OVR ((uint8_t)0x40) |
| #define | SPI_SR_BSY ((uint8_t)0x80) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | I2C_CR1_PE ((uint16_t)0x0001) |
| #define | I2C_CR1_SMBUS ((uint16_t)0x0002) |
| #define | I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
| #define | I2C_CR1_ENARP ((uint16_t)0x0010) |
| #define | I2C_CR1_ENPEC ((uint16_t)0x0020) |
| #define | I2C_CR1_ENGC ((uint16_t)0x0040) |
| #define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
| #define | I2C_CR1_START ((uint16_t)0x0100) |
| #define | I2C_CR1_STOP ((uint16_t)0x0200) |
| #define | I2C_CR1_ACK ((uint16_t)0x0400) |
| #define | I2C_CR1_POS ((uint16_t)0x0800) |
| #define | I2C_CR1_PEC ((uint16_t)0x1000) |
| #define | I2C_CR1_ALERT ((uint16_t)0x2000) |
| #define | I2C_CR1_SWRST ((uint16_t)0x8000) |
| #define | I2C_CR2_FREQ ((uint16_t)0x003F) |
| #define | I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
| #define | I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
| #define | I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
| #define | I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
| #define | I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
| #define | I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
| #define | I2C_CR2_ITERREN ((uint16_t)0x0100) |
| #define | I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
| #define | I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
| #define | I2C_CR2_DMAEN ((uint16_t)0x0800) |
| #define | I2C_CR2_LAST ((uint16_t)0x1000) |
| #define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
| #define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
| #define | I2C_OAR1_ADD0 ((uint16_t)0x0001) |
| #define | I2C_OAR1_ADD1 ((uint16_t)0x0002) |
| #define | I2C_OAR1_ADD2 ((uint16_t)0x0004) |
| #define | I2C_OAR1_ADD3 ((uint16_t)0x0008) |
| #define | I2C_OAR1_ADD4 ((uint16_t)0x0010) |
| #define | I2C_OAR1_ADD5 ((uint16_t)0x0020) |
| #define | I2C_OAR1_ADD6 ((uint16_t)0x0040) |
| #define | I2C_OAR1_ADD7 ((uint16_t)0x0080) |
| #define | I2C_OAR1_ADD8 ((uint16_t)0x0100) |
| #define | I2C_OAR1_ADD9 ((uint16_t)0x0200) |
| #define | I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
| #define | I2C_OAR2_ENDUAL ((uint8_t)0x01) |
| #define | I2C_OAR2_ADD2 ((uint8_t)0xFE) |
| #define | I2C_DR_DR ((uint8_t)0xFF) |
| #define | I2C_SR1_SB ((uint16_t)0x0001) |
| #define | I2C_SR1_ADDR ((uint16_t)0x0002) |
| #define | I2C_SR1_BTF ((uint16_t)0x0004) |
| #define | I2C_SR1_ADD10 ((uint16_t)0x0008) |
| #define | I2C_SR1_STOPF ((uint16_t)0x0010) |
| #define | I2C_SR1_RXNE ((uint16_t)0x0040) |
| #define | I2C_SR1_TXE ((uint16_t)0x0080) |
| #define | I2C_SR1_BERR ((uint16_t)0x0100) |
| #define | I2C_SR1_ARLO ((uint16_t)0x0200) |
| #define | I2C_SR1_AF ((uint16_t)0x0400) |
| #define | I2C_SR1_OVR ((uint16_t)0x0800) |
| #define | I2C_SR1_PECERR ((uint16_t)0x1000) |
| #define | I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
| #define | I2C_SR1_SMBALERT ((uint16_t)0x8000) |
| #define | I2C_SR2_MSL ((uint16_t)0x0001) |
| #define | I2C_SR2_BUSY ((uint16_t)0x0002) |
| #define | I2C_SR2_TRA ((uint16_t)0x0004) |
| #define | I2C_SR2_GENCALL ((uint16_t)0x0010) |
| #define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
| #define | I2C_SR2_SMBHOST ((uint16_t)0x0040) |
| #define | I2C_SR2_DUALF ((uint16_t)0x0080) |
| #define | I2C_SR2_PEC ((uint16_t)0xFF00) |
| #define | I2C_CCR_CCR ((uint16_t)0x0FFF) |
| #define | I2C_CCR_DUTY ((uint16_t)0x4000) |
| #define | I2C_CCR_FS ((uint16_t)0x8000) |
| #define | I2C_TRISE_TRISE ((uint8_t)0x3F) |
| #define | USART_SR_PE ((uint16_t)0x0001) |
| #define | USART_SR_FE ((uint16_t)0x0002) |
| #define | USART_SR_NE ((uint16_t)0x0004) |
| #define | USART_SR_ORE ((uint16_t)0x0008) |
| #define | USART_SR_IDLE ((uint16_t)0x0010) |
| #define | USART_SR_RXNE ((uint16_t)0x0020) |
| #define | USART_SR_TC ((uint16_t)0x0040) |
| #define | USART_SR_TXE ((uint16_t)0x0080) |
| #define | USART_SR_LBD ((uint16_t)0x0100) |
| #define | USART_SR_CTS ((uint16_t)0x0200) |
| #define | USART_DR_DR ((uint16_t)0x01FF) |
| #define | USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
| #define | USART_CR1_SBK ((uint16_t)0x0001) |
| #define | USART_CR1_RWU ((uint16_t)0x0002) |
| #define | USART_CR1_RE ((uint16_t)0x0004) |
| #define | USART_CR1_TE ((uint16_t)0x0008) |
| #define | USART_CR1_IDLEIE ((uint16_t)0x0010) |
| #define | USART_CR1_RXNEIE ((uint16_t)0x0020) |
| #define | USART_CR1_TCIE ((uint16_t)0x0040) |
| #define | USART_CR1_TXEIE ((uint16_t)0x0080) |
| #define | USART_CR1_PEIE ((uint16_t)0x0100) |
| #define | USART_CR1_PS ((uint16_t)0x0200) |
| #define | USART_CR1_PCE ((uint16_t)0x0400) |
| #define | USART_CR1_WAKE ((uint16_t)0x0800) |
| #define | USART_CR1_M ((uint16_t)0x1000) |
| #define | USART_CR1_UE ((uint16_t)0x2000) |
| #define | USART_CR1_OVER8 ((uint16_t)0x8000) |
| #define | USART_CR2_ADD ((uint16_t)0x000F) |
| #define | USART_CR2_LBDL ((uint16_t)0x0020) |
| #define | USART_CR2_LBDIE ((uint16_t)0x0040) |
| #define | USART_CR2_LBCL ((uint16_t)0x0100) |
| #define | USART_CR2_CPHA ((uint16_t)0x0200) |
| #define | USART_CR2_CPOL ((uint16_t)0x0400) |
| #define | USART_CR2_CLKEN ((uint16_t)0x0800) |
| #define | USART_CR2_STOP ((uint16_t)0x3000) |
| #define | USART_CR2_STOP_0 ((uint16_t)0x1000) |
| #define | USART_CR2_STOP_1 ((uint16_t)0x2000) |
| #define | USART_CR2_LINEN ((uint16_t)0x4000) |
| #define | USART_CR3_EIE ((uint16_t)0x0001) |
| #define | USART_CR3_IREN ((uint16_t)0x0002) |
| #define | USART_CR3_IRLP ((uint16_t)0x0004) |
| #define | USART_CR3_HDSEL ((uint16_t)0x0008) |
| #define | USART_CR3_NACK ((uint16_t)0x0010) |
| #define | USART_CR3_SCEN ((uint16_t)0x0020) |
| #define | USART_CR3_DMAR ((uint16_t)0x0040) |
| #define | USART_CR3_DMAT ((uint16_t)0x0080) |
| #define | USART_CR3_RTSE ((uint16_t)0x0100) |
| #define | USART_CR3_CTSE ((uint16_t)0x0200) |
| #define | USART_CR3_CTSIE ((uint16_t)0x0400) |
| #define | USART_CR3_ONEBIT ((uint16_t)0x0800) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_PSC_0 ((uint16_t)0x0001) |
| #define | USART_GTPR_PSC_1 ((uint16_t)0x0002) |
| #define | USART_GTPR_PSC_2 ((uint16_t)0x0004) |
| #define | USART_GTPR_PSC_3 ((uint16_t)0x0008) |
| #define | USART_GTPR_PSC_4 ((uint16_t)0x0010) |
| #define | USART_GTPR_PSC_5 ((uint16_t)0x0020) |
| #define | USART_GTPR_PSC_6 ((uint16_t)0x0040) |
| #define | USART_GTPR_PSC_7 ((uint16_t)0x0080) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) |
| #define | DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) |
| #define | DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
| #define | DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
| #define | DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) |
| #define | DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) |
| #define | DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) |
| #define | DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) |
| #define | DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) |
| #define | DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) |
| #define | DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) |
| #define | DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) |
| #define | DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) |
| #define | DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) |
| #define | DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) |
| #define | FLASH_ACR_LATENCY ((uint8_t)0x03) |
| #define | FLASH_ACR_LATENCY_0 ((uint8_t)0x00) |
| #define | FLASH_ACR_LATENCY_1 ((uint8_t)0x01) |
| #define | FLASH_ACR_LATENCY_2 ((uint8_t)0x02) |
| #define | FLASH_ACR_HLFCYA ((uint8_t)0x08) |
| #define | FLASH_ACR_PRFTBE ((uint8_t)0x10) |
| #define | FLASH_ACR_PRFTBS ((uint8_t)0x20) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_SR_BSY ((uint8_t)0x01) |
| #define | FLASH_SR_PGERR ((uint8_t)0x04) |
| #define | FLASH_SR_WRPRTERR ((uint8_t)0x10) |
| #define | FLASH_SR_EOP ((uint8_t)0x20) |
| #define | FLASH_CR_PG ((uint16_t)0x0001) |
| #define | FLASH_CR_PER ((uint16_t)0x0002) |
| #define | FLASH_CR_MER ((uint16_t)0x0004) |
| #define | FLASH_CR_OPTPG ((uint16_t)0x0010) |
| #define | FLASH_CR_OPTER ((uint16_t)0x0020) |
| #define | FLASH_CR_STRT ((uint16_t)0x0040) |
| #define | FLASH_CR_LOCK ((uint16_t)0x0080) |
| #define | FLASH_CR_OPTWRE ((uint16_t)0x0200) |
| #define | FLASH_CR_ERRIE ((uint16_t)0x0400) |
| #define | FLASH_CR_EOPIE ((uint16_t)0x1000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint16_t)0x0001) |
| #define | FLASH_OBR_RDPRT ((uint16_t)0x0002) |
| #define | FLASH_OBR_USER ((uint16_t)0x03FC) |
| #define | FLASH_OBR_WDG_SW ((uint16_t)0x0004) |
| #define | FLASH_OBR_nRST_STOP ((uint16_t)0x0008) |
| #define | FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) |
| #define | FLASH_OBR_BFB2 ((uint16_t)0x0020) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_RDP_RDP ((uint32_t)0x000000FF) |
| #define | FLASH_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | FLASH_USER_USER ((uint32_t)0x00FF0000) |
| #define | FLASH_USER_nUSER ((uint32_t)0xFF000000) |
| #define | FLASH_Data0_Data0 ((uint32_t)0x000000FF) |
| #define | FLASH_Data0_nData0 ((uint32_t)0x0000FF00) |
| #define | FLASH_Data1_Data1 ((uint32_t)0x00FF0000) |
| #define | FLASH_Data1_nData1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | ADC_ISR_ADRDY ((uint32_t)0x00000001) |
| #define | ADC_ISR_EOSMP ((uint32_t)0x00000002) |
| #define | ADC_ISR_EOC ((uint32_t)0x00000004) |
| #define | ADC_ISR_EOS ((uint32_t)0x00000008) |
| #define | ADC_ISR_OVR ((uint32_t)0x00000010) |
| #define | ADC_ISR_JEOC ((uint32_t)0x00000020) |
| #define | ADC_ISR_JEOS ((uint32_t)0x00000040) |
| #define | ADC_ISR_AWD1 ((uint32_t)0x00000080) |
| #define | ADC_ISR_AWD2 ((uint32_t)0x00000100) |
| #define | ADC_ISR_AWD3 ((uint32_t)0x00000200) |
| #define | ADC_ISR_JQOVF ((uint32_t)0x00000400) |
| #define | ADC_IER_RDY ((uint32_t)0x00000001) |
| #define | ADC_IER_EOSMP ((uint32_t)0x00000002) |
| #define | ADC_IER_EOC ((uint32_t)0x00000004) |
| #define | ADC_IER_EOS ((uint32_t)0x00000008) |
| #define | ADC_IER_OVR ((uint32_t)0x00000010) |
| #define | ADC_IER_JEOC ((uint32_t)0x00000020) |
| #define | ADC_IER_JEOS ((uint32_t)0x00000040) |
| #define | ADC_IER_AWD1 ((uint32_t)0x00000080) |
| #define | ADC_IER_AWD2 ((uint32_t)0x00000100) |
| #define | ADC_IER_AWD3 ((uint32_t)0x00000200) |
| #define | ADC_IER_JQOVF ((uint32_t)0x00000400) |
| #define | ADC_CR_ADEN ((uint32_t)0x00000001) |
| #define | ADC_CR_ADDIS ((uint32_t)0x00000002) |
| #define | ADC_CR_ADSTART ((uint32_t)0x00000004) |
| #define | ADC_CR_JADSTART ((uint32_t)0x00000008) |
| #define | ADC_CR_ADSTP ((uint32_t)0x00000010) |
| #define | ADC_CR_JADSTP ((uint32_t)0x00000020) |
| #define | ADC_CR_ADVREGEN ((uint32_t)0x30000000) |
| #define | ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) |
| #define | ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) |
| #define | ADC_CR_ADCALDIF ((uint32_t)0x40000000) |
| #define | ADC_CR_ADCAL ((uint32_t)0x80000000) |
| #define | ADC_CFGR_DMAEN ((uint32_t)0x00000001) |
| #define | ADC_CFGR_DMACFG ((uint32_t)0x00000002) |
| #define | ADC_CFGR_RES ((uint32_t)0x00000018) |
| #define | ADC_CFGR_RES_0 ((uint32_t)0x00000008) |
| #define | ADC_CFGR_RES_1 ((uint32_t)0x00000010) |
| #define | ADC_CFGR_ALIGN ((uint32_t)0x00000020) |
| #define | ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) |
| #define | ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) |
| #define | ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) |
| #define | ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) |
| #define | ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) |
| #define | ADC_CFGR_EXTEN ((uint32_t)0x00000C00) |
| #define | ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) |
| #define | ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) |
| #define | ADC_CFGR_OVRMOD ((uint32_t)0x00001000) |
| #define | ADC_CFGR_CONT ((uint32_t)0x00002000) |
| #define | ADC_CFGR_AUTDLY ((uint32_t)0x00004000) |
| #define | ADC_CFGR_AUTOFF ((uint32_t)0x00008000) |
| #define | ADC_CFGR_DISCEN ((uint32_t)0x00010000) |
| #define | ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) |
| #define | ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) |
| #define | ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) |
| #define | ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) |
| #define | ADC_CFGR_JDISCEN ((uint32_t)0x00100000) |
| #define | ADC_CFGR_JQM ((uint32_t)0x00200000) |
| #define | ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) |
| #define | ADC_CFGR_AWD1EN ((uint32_t)0x00800000) |
| #define | ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) |
| #define | ADC_CFGR_JAUTO ((uint32_t)0x02000000) |
| #define | ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) |
| #define | ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) |
| #define | ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) |
| #define | ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) |
| #define | ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) |
| #define | ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) |
| #define | ADC_SMPR1_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR1_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_SMPR2_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP18 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) |
| #define | ADC_TR1_LT1 ((uint32_t)0x00000FFF) |
| #define | ADC_TR1_LT1_0 ((uint32_t)0x00000001) |
| #define | ADC_TR1_LT1_1 ((uint32_t)0x00000002) |
| #define | ADC_TR1_LT1_2 ((uint32_t)0x00000004) |
| #define | ADC_TR1_LT1_3 ((uint32_t)0x00000008) |
| #define | ADC_TR1_LT1_4 ((uint32_t)0x00000010) |
| #define | ADC_TR1_LT1_5 ((uint32_t)0x00000020) |
| #define | ADC_TR1_LT1_6 ((uint32_t)0x00000040) |
| #define | ADC_TR1_LT1_7 ((uint32_t)0x00000080) |
| #define | ADC_TR1_LT1_8 ((uint32_t)0x00000100) |
| #define | ADC_TR1_LT1_9 ((uint32_t)0x00000200) |
| #define | ADC_TR1_LT1_10 ((uint32_t)0x00000400) |
| #define | ADC_TR1_LT1_11 ((uint32_t)0x00000800) |
| #define | ADC_TR1_HT1 ((uint32_t)0x0FFF0000) |
| #define | ADC_TR1_HT1_0 ((uint32_t)0x00010000) |
| #define | ADC_TR1_HT1_1 ((uint32_t)0x00020000) |
| #define | ADC_TR1_HT1_2 ((uint32_t)0x00040000) |
| #define | ADC_TR1_HT1_3 ((uint32_t)0x00080000) |
| #define | ADC_TR1_HT1_4 ((uint32_t)0x00100000) |
| #define | ADC_TR1_HT1_5 ((uint32_t)0x00200000) |
| #define | ADC_TR1_HT1_6 ((uint32_t)0x00400000) |
| #define | ADC_TR1_HT1_7 ((uint32_t)0x00800000) |
| #define | ADC_TR1_HT1_8 ((uint32_t)0x01000000) |
| #define | ADC_TR1_HT1_9 ((uint32_t)0x02000000) |
| #define | ADC_TR1_HT1_10 ((uint32_t)0x04000000) |
| #define | ADC_TR1_HT1_11 ((uint32_t)0x08000000) |
| #define | ADC_TR2_LT2 ((uint32_t)0x000000FF) |
| #define | ADC_TR2_LT2_0 ((uint32_t)0x00000001) |
| #define | ADC_TR2_LT2_1 ((uint32_t)0x00000002) |
| #define | ADC_TR2_LT2_2 ((uint32_t)0x00000004) |
| #define | ADC_TR2_LT2_3 ((uint32_t)0x00000008) |
| #define | ADC_TR2_LT2_4 ((uint32_t)0x00000010) |
| #define | ADC_TR2_LT2_5 ((uint32_t)0x00000020) |
| #define | ADC_TR2_LT2_6 ((uint32_t)0x00000040) |
| #define | ADC_TR2_LT2_7 ((uint32_t)0x00000080) |
| #define | ADC_TR2_HT2 ((uint32_t)0x00FF0000) |
| #define | ADC_TR2_HT2_0 ((uint32_t)0x00010000) |
| #define | ADC_TR2_HT2_1 ((uint32_t)0x00020000) |
| #define | ADC_TR2_HT2_2 ((uint32_t)0x00040000) |
| #define | ADC_TR2_HT2_3 ((uint32_t)0x00080000) |
| #define | ADC_TR2_HT2_4 ((uint32_t)0x00100000) |
| #define | ADC_TR2_HT2_5 ((uint32_t)0x00200000) |
| #define | ADC_TR2_HT2_6 ((uint32_t)0x00400000) |
| #define | ADC_TR2_HT2_7 ((uint32_t)0x00800000) |
| #define | ADC_TR3_LT3 ((uint32_t)0x000000FF) |
| #define | ADC_TR3_LT3_0 ((uint32_t)0x00000001) |
| #define | ADC_TR3_LT3_1 ((uint32_t)0x00000002) |
| #define | ADC_TR3_LT3_2 ((uint32_t)0x00000004) |
| #define | ADC_TR3_LT3_3 ((uint32_t)0x00000008) |
| #define | ADC_TR3_LT3_4 ((uint32_t)0x00000010) |
| #define | ADC_TR3_LT3_5 ((uint32_t)0x00000020) |
| #define | ADC_TR3_LT3_6 ((uint32_t)0x00000040) |
| #define | ADC_TR3_LT3_7 ((uint32_t)0x00000080) |
| #define | ADC_TR3_HT3 ((uint32_t)0x00FF0000) |
| #define | ADC_TR3_HT3_0 ((uint32_t)0x00010000) |
| #define | ADC_TR3_HT3_1 ((uint32_t)0x00020000) |
| #define | ADC_TR3_HT3_2 ((uint32_t)0x00040000) |
| #define | ADC_TR3_HT3_3 ((uint32_t)0x00080000) |
| #define | ADC_TR3_HT3_4 ((uint32_t)0x00100000) |
| #define | ADC_TR3_HT3_5 ((uint32_t)0x00200000) |
| #define | ADC_TR3_HT3_6 ((uint32_t)0x00400000) |
| #define | ADC_TR3_HT3_7 ((uint32_t)0x00800000) |
| #define | ADC_SQR1_L ((uint32_t)0x0000000F) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ1 ((uint32_t)0x000007C0) |
| #define | ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ2 ((uint32_t)0x0001F000) |
| #define | ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ3 ((uint32_t)0x007C0000) |
| #define | ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_SQ4 ((uint32_t)0x1F000000) |
| #define | ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) |
| #define | ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) |
| #define | ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) |
| #define | ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) |
| #define | ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ5 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ6 ((uint32_t)0x000007C0) |
| #define | ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0001F000) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x007C0000) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x1F000000) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ10 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ11 ((uint32_t)0x000007C0) |
| #define | ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ12 ((uint32_t)0x0001F000) |
| #define | ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ13 ((uint32_t)0x007C0000) |
| #define | ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ14 ((uint32_t)0x1F000000) |
| #define | ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ15 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ15_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ15_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ15_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ15_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ15_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ16 ((uint32_t)0x000007C0) |
| #define | ADC_SQR3_SQ16_0 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ16_1 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ16_2 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ16_3 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ16_4 ((uint32_t)0x00000400) |
| #define | ADC_DR_RDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_RDATA_0 ((uint32_t)0x00000001) |
| #define | ADC_DR_RDATA_1 ((uint32_t)0x00000002) |
| #define | ADC_DR_RDATA_2 ((uint32_t)0x00000004) |
| #define | ADC_DR_RDATA_3 ((uint32_t)0x00000008) |
| #define | ADC_DR_RDATA_4 ((uint32_t)0x00000010) |
| #define | ADC_DR_RDATA_5 ((uint32_t)0x00000020) |
| #define | ADC_DR_RDATA_6 ((uint32_t)0x00000040) |
| #define | ADC_DR_RDATA_7 ((uint32_t)0x00000080) |
| #define | ADC_DR_RDATA_8 ((uint32_t)0x00000100) |
| #define | ADC_DR_RDATA_9 ((uint32_t)0x00000200) |
| #define | ADC_DR_RDATA_10 ((uint32_t)0x00000400) |
| #define | ADC_DR_RDATA_11 ((uint32_t)0x00000800) |
| #define | ADC_DR_RDATA_12 ((uint32_t)0x00001000) |
| #define | ADC_DR_RDATA_13 ((uint32_t)0x00002000) |
| #define | ADC_DR_RDATA_14 ((uint32_t)0x00004000) |
| #define | ADC_DR_RDATA_15 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00000003) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) |
| #define | ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) |
| #define | ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) |
| #define | ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) |
| #define | ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) |
| #define | ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) |
| #define | ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) |
| #define | ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) |
| #define | ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) |
| #define | ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) |
| #define | ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) |
| #define | ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) |
| #define | ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) |
| #define | ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) |
| #define | ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) |
| #define | ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) |
| #define | ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) |
| #define | ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) |
| #define | ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) |
| #define | ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) |
| #define | ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) |
| #define | ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) |
| #define | ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) |
| #define | ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) |
| #define | ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) |
| #define | ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) |
| #define | ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) |
| #define | ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) |
| #define | ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) |
| #define | ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) |
| #define | ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) |
| #define | ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) |
| #define | ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) |
| #define | ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) |
| #define | ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) |
| #define | ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) |
| #define | ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) |
| #define | ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) |
| #define | ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) |
| #define | ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) |
| #define | ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) |
| #define | ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) |
| #define | ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) |
| #define | ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) |
| #define | ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) |
| #define | ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) |
| #define | ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) |
| #define | ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) |
| #define | ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) |
| #define | ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) |
| #define | ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) |
| #define | ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) |
| #define | ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) |
| #define | ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) |
| #define | ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) |
| #define | ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) |
| #define | ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) |
| #define | ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) |
| #define | ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) |
| #define | ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) |
| #define | ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) |
| #define | ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) |
| #define | ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) |
| #define | ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) |
| #define | ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) |
| #define | ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) |
| #define | ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) |
| #define | ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) |
| #define | ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) |
| #define | ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) |
| #define | ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) |
| #define | ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) |
| #define | ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) |
| #define | ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) |
| #define | ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) |
| #define | ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) |
| #define | ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) |
| #define | ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) |
| #define | ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) |
| #define | ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) |
| #define | ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) |
| #define | ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) |
| #define | ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) |
| #define | ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) |
| #define | ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) |
| #define | ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) |
| #define | ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) |
| #define | ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) |
| #define | ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) |
| #define | ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) |
| #define | ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) |
| #define | ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) |
| #define | ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) |
| #define | ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) |
| #define | ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) |
| #define | ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) |
| #define | ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) |
| #define | ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) |
| #define | ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) |
| #define | ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) |
| #define | ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) |
| #define | ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) |
| #define | ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) |
| #define | ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) |
| #define | ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) |
| #define | ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) |
| #define | ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) |
| #define | ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) |
| #define | ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) |
| #define | ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) |
| #define | ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) |
| #define | ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) |
| #define | ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) |
| #define | ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) |
| #define | ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) |
| #define | ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) |
| #define | ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) |
| #define | ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) |
| #define | ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) |
| #define | ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) |
| #define | ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) |
| #define | ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) |
| #define | ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) |
| #define | ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) |
| #define | ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) |
| #define | ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) |
| #define | ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) |
| #define | ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) |
| #define | ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) |
| #define | ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) |
| #define | ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) |
| #define | ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) |
| #define | ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) |
| #define | ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) |
| #define | ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) |
| #define | ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) |
| #define | ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) |
| #define | ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) |
| #define | ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) |
| #define | ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) |
| #define | ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) |
| #define | ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) |
| #define | ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) |
| #define | ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) |
| #define | ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) |
| #define | ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) |
| #define | ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) |
| #define | ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) |
| #define | ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) |
| #define | ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) |
| #define | ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) |
| #define | ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) |
| #define | ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) |
| #define | ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) |
| #define | ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) |
| #define | ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) |
| #define | ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) |
| #define | ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) |
| #define | ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) |
| #define | ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) |
| #define | ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) |
| #define | ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) |
| #define | ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) |
| #define | ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) |
| #define | ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) |
| #define | ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) |
| #define | ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) |
| #define | ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) |
| #define | ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) |
| #define | ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) |
| #define | ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) |
| #define | ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) |
| #define | ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) |
| #define | ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) |
| #define | ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) |
| #define | ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) |
| #define | ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) |
| #define | ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) |
| #define | ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) |
| #define | ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) |
| #define | ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) |
| #define | ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) |
| #define | ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) |
| #define | ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) |
| #define | ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) |
| #define | ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) |
| #define | ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) |
| #define | ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) |
| #define | ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) |
| #define | ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) |
| #define | ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) |
| #define | ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) |
| #define | ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) |
| #define | ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) |
| #define | ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) |
| #define | ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) |
| #define | ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) |
| #define | ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) |
| #define | ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) |
| #define | ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) |
| #define | ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) |
| #define | ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) |
| #define | ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) |
| #define | ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) |
| #define | ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) |
| #define | ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) |
| #define | ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) |
| #define | ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) |
| #define | ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) |
| #define | ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) |
| #define | ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) |
| #define | ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) |
| #define | ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) |
| #define | ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) |
| #define | ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) |
| #define | ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) |
| #define | ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) |
| #define | ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) |
| #define | ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) |
| #define | ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) |
| #define | ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) |
| #define | ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) |
| #define | ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) |
| #define | ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) |
| #define | ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) |
| #define | ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) |
| #define | ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) |
| #define | ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) |
| #define | ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) |
| #define | ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) |
| #define | ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) |
| #define | ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) |
| #define | ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) |
| #define | ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) |
| #define | ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) |
| #define | ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) |
| #define | ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) |
| #define | ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) |
| #define | ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) |
| #define | ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) |
| #define | ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) |
| #define | ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) |
| #define | ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) |
| #define | ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) |
| #define | ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) |
| #define | ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) |
| #define | ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) |
| #define | ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) |
| #define | ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) |
| #define | ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) |
| #define | ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) |
| #define | ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) |
| #define | ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) |
| #define | ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) |
| #define | ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) |
| #define | ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) |
| #define | ADC12_CCR_MULTI ((uint32_t)0x0000001F) |
| #define | ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) |
| #define | ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) |
| #define | ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) |
| #define | ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) |
| #define | ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) |
| #define | ADC12_CCR_DELAY ((uint32_t)0x00000F00) |
| #define | ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) |
| #define | ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) |
| #define | ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) |
| #define | ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) |
| #define | ADC12_CCR_DMACFG ((uint32_t)0x00002000) |
| #define | ADC12_CCR_MDMA ((uint32_t)0x0000C000) |
| #define | ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) |
| #define | ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) |
| #define | ADC12_CCR_CKMODE ((uint32_t)0x00030000) |
| #define | ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) |
| #define | ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) |
| #define | ADC12_CCR_VREFEN ((uint32_t)0x00400000) |
| #define | ADC12_CCR_TSEN ((uint32_t)0x00800000) |
| #define | ADC12_CCR_VBATEN ((uint32_t)0x01000000) |
| #define | ADC34_CCR_MULTI ((uint32_t)0x0000001F) |
| #define | ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) |
| #define | ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) |
| #define | ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) |
| #define | ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) |
| #define | ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) |
| #define | ADC34_CCR_DELAY ((uint32_t)0x00000F00) |
| #define | ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) |
| #define | ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) |
| #define | ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) |
| #define | ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) |
| #define | ADC34_CCR_DMACFG ((uint32_t)0x00002000) |
| #define | ADC34_CCR_MDMA ((uint32_t)0x0000C000) |
| #define | ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) |
| #define | ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) |
| #define | ADC34_CCR_CKMODE ((uint32_t)0x00030000) |
| #define | ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) |
| #define | ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) |
| #define | ADC34_CCR_VREFEN ((uint32_t)0x00400000) |
| #define | ADC34_CCR_TSEN ((uint32_t)0x00800000) |
| #define | ADC34_CCR_VBATEN ((uint32_t)0x01000000) |
| #define | ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) |
| #define | ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) |
| #define | ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) |
| #define | ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) |
| #define | ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) |
| #define | ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) |
| #define | ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) |
| #define | ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) |
| #define | ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) |
| #define | ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) |
| #define | ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) |
| #define | ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) |
| #define | ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) |
| #define | ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) |
| #define | ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) |
| #define | ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) |
| #define | ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) |
| #define | ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) |
| #define | ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) |
| #define | ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) |
| #define | ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) |
| #define | ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) |
| #define | ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) |
| #define | ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) |
| #define | ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) |
| #define | ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) |
| #define | ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) |
| #define | ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) |
| #define | ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) |
| #define | ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) |
| #define | ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) |
| #define | ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) |
| #define | ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) |
| #define | ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) |
| #define | ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) |
| #define | ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) |
| #define | ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) |
| #define | ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) |
| #define | ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) |
| #define | ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) |
| #define | ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) |
| #define | ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) |
| #define | ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) |
| #define | ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) |
| #define | ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) |
| #define | ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) |
| #define | ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) |
| #define | ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) |
| #define | ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) |
| #define | ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) |
| #define | ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) |
| #define | ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) |
| #define | ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) |
| #define | ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) |
| #define | ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) |
| #define | ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) |
| #define | ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) |
| #define | ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) |
| #define | ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) |
| #define | ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) |
| #define | ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) |
| #define | ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) |
| #define | ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) |
| #define | ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) |
| #define | ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) |
| #define | ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) |
| #define | ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) |
| #define | ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) |
| #define | COMP1_CSR_COMP1EN ((uint32_t)0x00000001) |
| #define | COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) |
| #define | COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) |
| #define | COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) |
| #define | COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) |
| #define | COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) |
| #define | COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) |
| #define | COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) |
| #define | COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP1_CSR_COMP1POL ((uint32_t)0x00008000) |
| #define | COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) |
| #define | COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) |
| #define | COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) |
| #define | COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) |
| #define | COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) |
| #define | COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) |
| #define | COMP2_CSR_COMP2EN ((uint32_t)0x00000001) |
| #define | COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) |
| #define | COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) |
| #define | COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) |
| #define | COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) |
| #define | COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) |
| #define | COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) |
| #define | COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) |
| #define | COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP2_CSR_COMP2POL ((uint32_t)0x00008000) |
| #define | COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) |
| #define | COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) |
| #define | COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) |
| #define | COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) |
| #define | COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) |
| #define | COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) |
| #define | COMP3_CSR_COMP3EN ((uint32_t)0x00000001) |
| #define | COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) |
| #define | COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) |
| #define | COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) |
| #define | COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) |
| #define | COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) |
| #define | COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) |
| #define | COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP3_CSR_COMP3POL ((uint32_t)0x00008000) |
| #define | COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) |
| #define | COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) |
| #define | COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) |
| #define | COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) |
| #define | COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) |
| #define | COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) |
| #define | COMP4_CSR_COMP4EN ((uint32_t)0x00000001) |
| #define | COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) |
| #define | COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) |
| #define | COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) |
| #define | COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) |
| #define | COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) |
| #define | COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) |
| #define | COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) |
| #define | COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP4_CSR_COMP4POL ((uint32_t)0x00008000) |
| #define | COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) |
| #define | COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) |
| #define | COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) |
| #define | COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) |
| #define | COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) |
| #define | COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) |
| #define | COMP5_CSR_COMP5EN ((uint32_t)0x00000001) |
| #define | COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) |
| #define | COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) |
| #define | COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) |
| #define | COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) |
| #define | COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) |
| #define | COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) |
| #define | COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP5_CSR_COMP5POL ((uint32_t)0x00008000) |
| #define | COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) |
| #define | COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) |
| #define | COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) |
| #define | COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) |
| #define | COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) |
| #define | COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) |
| #define | COMP6_CSR_COMP6EN ((uint32_t)0x00000001) |
| #define | COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) |
| #define | COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) |
| #define | COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) |
| #define | COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) |
| #define | COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) |
| #define | COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) |
| #define | COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) |
| #define | COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP6_CSR_COMP6POL ((uint32_t)0x00008000) |
| #define | COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) |
| #define | COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) |
| #define | COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) |
| #define | COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) |
| #define | COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) |
| #define | COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) |
| #define | COMP7_CSR_COMP7EN ((uint32_t)0x00000001) |
| #define | COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) |
| #define | COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) |
| #define | COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) |
| #define | COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) |
| #define | COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) |
| #define | COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) |
| #define | COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP7_CSR_COMP7POL ((uint32_t)0x00008000) |
| #define | COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) |
| #define | COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) |
| #define | COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) |
| #define | COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) |
| #define | COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) |
| #define | COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) |
| #define | COMP_CSR_COMPxEN ((uint32_t)0x00000001) |
| #define | COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) |
| #define | COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) |
| #define | COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) |
| #define | COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) |
| #define | COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) |
| #define | COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) |
| #define | COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) |
| #define | COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) |
| #define | COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) |
| #define | COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) |
| #define | COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) |
| #define | COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) |
| #define | COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) |
| #define | COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) |
| #define | COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) |
| #define | COMP_CSR_COMPxPOL ((uint32_t)0x00008000) |
| #define | COMP_CSR_COMPxHYST ((uint32_t)0x00030000) |
| #define | COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) |
| #define | COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) |
| #define | COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) |
| #define | COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) |
| #define | COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) |
| #define | COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) |
| #define | COMP_CSR_COMPxOUT ((uint32_t)0x40000000) |
| #define | COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) |
| #define | OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) |
| #define | OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) |
| #define | OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) |
| #define | OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) |
| #define | OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) |
| #define | OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) |
| #define | OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) |
| #define | OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) |
| #define | OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) |
| #define | OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) |
| #define | OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) |
| #define | OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) |
| #define | OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) |
| #define | OPAMP1_CSR_CALON ((uint32_t)0x00000800) |
| #define | OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) |
| #define | OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) |
| #define | OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) |
| #define | OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) |
| #define | OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) |
| #define | OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) |
| #define | OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) |
| #define | OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) |
| #define | OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) |
| #define | OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) |
| #define | OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) |
| #define | OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) |
| #define | OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) |
| #define | OPAMP1_CSR_LOCK ((uint32_t)0x80000000) |
| #define | OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) |
| #define | OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) |
| #define | OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) |
| #define | OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) |
| #define | OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) |
| #define | OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) |
| #define | OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) |
| #define | OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) |
| #define | OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) |
| #define | OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) |
| #define | OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) |
| #define | OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) |
| #define | OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) |
| #define | OPAMP2_CSR_CALON ((uint32_t)0x00000800) |
| #define | OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) |
| #define | OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) |
| #define | OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) |
| #define | OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) |
| #define | OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) |
| #define | OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) |
| #define | OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) |
| #define | OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) |
| #define | OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) |
| #define | OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) |
| #define | OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) |
| #define | OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) |
| #define | OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) |
| #define | OPAMP2_CSR_LOCK ((uint32_t)0x80000000) |
| #define | OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) |
| #define | OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) |
| #define | OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) |
| #define | OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) |
| #define | OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) |
| #define | OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) |
| #define | OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) |
| #define | OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) |
| #define | OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) |
| #define | OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) |
| #define | OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) |
| #define | OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) |
| #define | OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) |
| #define | OPAMP3_CSR_CALON ((uint32_t)0x00000800) |
| #define | OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) |
| #define | OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) |
| #define | OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) |
| #define | OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) |
| #define | OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) |
| #define | OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) |
| #define | OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) |
| #define | OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) |
| #define | OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) |
| #define | OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) |
| #define | OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) |
| #define | OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) |
| #define | OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) |
| #define | OPAMP3_CSR_LOCK ((uint32_t)0x80000000) |
| #define | OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) |
| #define | OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) |
| #define | OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) |
| #define | OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) |
| #define | OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) |
| #define | OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) |
| #define | OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) |
| #define | OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) |
| #define | OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) |
| #define | OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) |
| #define | OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) |
| #define | OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) |
| #define | OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) |
| #define | OPAMP4_CSR_CALON ((uint32_t)0x00000800) |
| #define | OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) |
| #define | OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) |
| #define | OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) |
| #define | OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) |
| #define | OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) |
| #define | OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) |
| #define | OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) |
| #define | OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) |
| #define | OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) |
| #define | OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) |
| #define | OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) |
| #define | OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) |
| #define | OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) |
| #define | OPAMP4_CSR_LOCK ((uint32_t)0x80000000) |
| #define | OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) |
| #define | OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) |
| #define | OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) |
| #define | OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) |
| #define | OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) |
| #define | OPAMP_CSR_VMSEL ((uint32_t)0x00000060) |
| #define | OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) |
| #define | OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) |
| #define | OPAMP_CSR_TCMEN ((uint32_t)0x00000080) |
| #define | OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) |
| #define | OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) |
| #define | OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) |
| #define | OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) |
| #define | OPAMP_CSR_CALON ((uint32_t)0x00000800) |
| #define | OPAMP_CSR_CALSEL ((uint32_t)0x00003000) |
| #define | OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) |
| #define | OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) |
| #define | OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) |
| #define | OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) |
| #define | OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) |
| #define | OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) |
| #define | OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) |
| #define | OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) |
| #define | OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) |
| #define | OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) |
| #define | OPAMP_CSR_TSTREF ((uint32_t)0x20000000) |
| #define | OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) |
| #define | OPAMP_CSR_LOCK ((uint32_t)0x80000000) |
| #define | CAN_MCR_INRQ ((uint16_t)0x0001) |
| #define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
| #define | CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define | CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define | CAN_MCR_NART ((uint16_t)0x0010) |
| #define | CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define | CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define | CAN_MCR_TTCM ((uint16_t)0x0080) |
| #define | CAN_MCR_RESET ((uint16_t)0x8000) |
| #define | CAN_MSR_INAK ((uint16_t)0x0001) |
| #define | CAN_MSR_SLAK ((uint16_t)0x0002) |
| #define | CAN_MSR_ERRI ((uint16_t)0x0004) |
| #define | CAN_MSR_WKUI ((uint16_t)0x0008) |
| #define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
| #define | CAN_MSR_TXM ((uint16_t)0x0100) |
| #define | CAN_MSR_RXM ((uint16_t)0x0200) |
| #define | CAN_MSR_SAMP ((uint16_t)0x0400) |
| #define | CAN_MSR_RX ((uint16_t)0x0800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
| #define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
| #define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
| #define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
| #define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
| #define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
| #define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
| #define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint8_t)0x01) |
| #define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
| #define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
| #define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
| #define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
| #define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
| #define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
| #define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
| #define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
| #define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
| #define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
| #define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
| #define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
| #define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
| #define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
| #define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
| #define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
| #define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
| #define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
| #define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
| #define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
| #define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
| #define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
| #define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
| #define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
| #define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
| #define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
| #define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
| #define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
| #define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
| #define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
| #define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
| #define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
| #define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
| #define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
| #define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
| #define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
| #define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
| #define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
| #define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
| #define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
| #define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
| #define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
| #define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
| #define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
| #define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
| #define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
| #define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
| #define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
| #define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
| #define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
| #define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
| #define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
| #define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
| #define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
| #define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
| #define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
| #define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
| #define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
| #define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
| #define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | CRC_CR_POLSIZE ((uint32_t)0x00000018) |
| #define | CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) |
| #define | CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) |
| #define | CRC_CR_REV_IN ((uint32_t)0x00000060) |
| #define | CRC_CR_REV_IN_0 ((uint32_t)0x00000020) |
| #define | CRC_CR_REV_IN_1 ((uint32_t)0x00000040) |
| #define | CRC_CR_REV_OUT ((uint32_t)0x00000080) |
| #define | CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) |
| #define | CRC_POL_POL ((uint32_t)0xFFFFFFFF) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_IMR_MR20 ((uint32_t)0x00100000) |
| #define | EXTI_IMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_IMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_IMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_IMR_MR24 ((uint32_t)0x01000000) |
| #define | EXTI_IMR_MR25 ((uint32_t)0x02000000) |
| #define | EXTI_IMR_MR26 ((uint32_t)0x04000000) |
| #define | EXTI_IMR_MR27 ((uint32_t)0x08000000) |
| #define | EXTI_IMR_MR28 ((uint32_t)0x10000000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR20 ((uint32_t)0x00100000) |
| #define | EXTI_EMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_EMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_EMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_EMR_MR24 ((uint32_t)0x01000000) |
| #define | EXTI_EMR_MR25 ((uint32_t)0x02000000) |
| #define | EXTI_EMR_MR26 ((uint32_t)0x04000000) |
| #define | EXTI_EMR_MR27 ((uint32_t)0x08000000) |
| #define | EXTI_EMR_MR28 ((uint32_t)0x10000000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR20 ((uint32_t)0x00100000) |
| #define | EXTI_RTSR_TR21 ((uint32_t)0x00200000) |
| #define | EXTI_RTSR_TR22 ((uint32_t)0x00400000) |
| #define | EXTI_RTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_RTSR_TR24 ((uint32_t)0x01000000) |
| #define | EXTI_RTSR_TR25 ((uint32_t)0x02000000) |
| #define | EXTI_RTSR_TR26 ((uint32_t)0x04000000) |
| #define | EXTI_RTSR_TR27 ((uint32_t)0x08000000) |
| #define | EXTI_RTSR_TR28 ((uint32_t)0x10000000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR20 ((uint32_t)0x00100000) |
| #define | EXTI_FTSR_TR21 ((uint32_t)0x00200000) |
| #define | EXTI_FTSR_TR22 ((uint32_t)0x00400000) |
| #define | EXTI_FTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_FTSR_TR24 ((uint32_t)0x01000000) |
| #define | EXTI_FTSR_TR25 ((uint32_t)0x02000000) |
| #define | EXTI_FTSR_TR26 ((uint32_t)0x04000000) |
| #define | EXTI_FTSR_TR27 ((uint32_t)0x08000000) |
| #define | EXTI_FTSR_TR28 ((uint32_t)0x10000000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) |
| #define | EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) |
| #define | EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) |
| #define | EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) |
| #define | EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) |
| #define | EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) |
| #define | EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) |
| #define | EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) |
| #define | EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR20 ((uint32_t)0x00100000) |
| #define | EXTI_PR_PR21 ((uint32_t)0x00200000) |
| #define | EXTI_PR_PR22 ((uint32_t)0x00400000) |
| #define | EXTI_PR_PR23 ((uint32_t)0x00800000) |
| #define | EXTI_PR_PR24 ((uint32_t)0x01000000) |
| #define | EXTI_PR_PR25 ((uint32_t)0x02000000) |
| #define | EXTI_PR_PR26 ((uint32_t)0x04000000) |
| #define | EXTI_PR_PR27 ((uint32_t)0x08000000) |
| #define | EXTI_PR_PR28 ((uint32_t)0x10000000) |
| #define | FLASH_ACR_LATENCY ((uint8_t)0x03) |
| #define | FLASH_ACR_LATENCY_0 ((uint8_t)0x01) |
| #define | FLASH_ACR_LATENCY_1 ((uint8_t)0x02) |
| #define | FLASH_ACR_HLFCYA ((uint8_t)0x08) |
| #define | FLASH_ACR_PRFTBE ((uint8_t)0x10) |
| #define | FLASH_ACR_PRFTBS ((uint8_t)0x20) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | RDP_KEY ((uint16_t)0x00A5) |
| #define | FLASH_KEY1 ((uint32_t)0x45670123) |
| #define | FLASH_KEY2 ((uint32_t)0xCDEF89AB) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEY1 FLASH_KEY1 |
| #define | FLASH_OPTKEY2 FLASH_KEY2 |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) |
| #define | FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) |
| #define | FLASH_OBR_USER ((uint32_t)0x00003700) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | OB_RDP_RDP ((uint32_t)0x000000FF) |
| #define | OB_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | OB_USER_USER ((uint32_t)0x00FF0000) |
| #define | OB_USER_nUSER ((uint32_t)0xFF000000) |
| #define | OB_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | OB_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | OB_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | OB_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | OB_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | OB_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) |
| #define | GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) |
| #define | GPIO_BRR_BR_0 ((uint32_t)0x00000001) |
| #define | GPIO_BRR_BR_1 ((uint32_t)0x00000002) |
| #define | GPIO_BRR_BR_2 ((uint32_t)0x00000004) |
| #define | GPIO_BRR_BR_3 ((uint32_t)0x00000008) |
| #define | GPIO_BRR_BR_4 ((uint32_t)0x00000010) |
| #define | GPIO_BRR_BR_5 ((uint32_t)0x00000020) |
| #define | GPIO_BRR_BR_6 ((uint32_t)0x00000040) |
| #define | GPIO_BRR_BR_7 ((uint32_t)0x00000080) |
| #define | GPIO_BRR_BR_8 ((uint32_t)0x00000100) |
| #define | GPIO_BRR_BR_9 ((uint32_t)0x00000200) |
| #define | GPIO_BRR_BR_10 ((uint32_t)0x00000400) |
| #define | GPIO_BRR_BR_11 ((uint32_t)0x00000800) |
| #define | GPIO_BRR_BR_12 ((uint32_t)0x00001000) |
| #define | GPIO_BRR_BR_13 ((uint32_t)0x00002000) |
| #define | GPIO_BRR_BR_14 ((uint32_t)0x00004000) |
| #define | GPIO_BRR_BR_15 ((uint32_t)0x00008000) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_TXIE ((uint32_t)0x00000002) |
| #define | I2C_CR1_RXIE ((uint32_t)0x00000004) |
| #define | I2C_CR1_ADDRIE ((uint32_t)0x00000008) |
| #define | I2C_CR1_NACKIE ((uint32_t)0x00000010) |
| #define | I2C_CR1_STOPIE ((uint32_t)0x00000020) |
| #define | I2C_CR1_TCIE ((uint32_t)0x00000040) |
| #define | I2C_CR1_ERRIE ((uint32_t)0x00000080) |
| #define | I2C_CR1_DFN ((uint32_t)0x00000F00) |
| #define | I2C_CR1_ANFOFF ((uint32_t)0x00001000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00002000) |
| #define | I2C_CR1_TXDMAEN ((uint32_t)0x00004000) |
| #define | I2C_CR1_RXDMAEN ((uint32_t)0x00008000) |
| #define | I2C_CR1_SBC ((uint32_t)0x00010000) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) |
| #define | I2C_CR1_WUPEN ((uint32_t)0x00040000) |
| #define | I2C_CR1_GCEN ((uint32_t)0x00080000) |
| #define | I2C_CR1_SMBHEN ((uint32_t)0x00100000) |
| #define | I2C_CR1_SMBDEN ((uint32_t)0x00200000) |
| #define | I2C_CR1_ALERTEN ((uint32_t)0x00400000) |
| #define | I2C_CR1_PECEN ((uint32_t)0x00800000) |
| #define | I2C_CR2_SADD ((uint32_t)0x000003FF) |
| #define | I2C_CR2_RD_WRN ((uint32_t)0x00000400) |
| #define | I2C_CR2_ADD10 ((uint32_t)0x00000800) |
| #define | I2C_CR2_HEAD10R ((uint32_t)0x00001000) |
| #define | I2C_CR2_START ((uint32_t)0x00002000) |
| #define | I2C_CR2_STOP ((uint32_t)0x00004000) |
| #define | I2C_CR2_NACK ((uint32_t)0x00008000) |
| #define | I2C_CR2_NBYTES ((uint32_t)0x00FF0000) |
| #define | I2C_CR2_RELOAD ((uint32_t)0x01000000) |
| #define | I2C_CR2_AUTOEND ((uint32_t)0x02000000) |
| #define | I2C_CR2_PECBYTE ((uint32_t)0x04000000) |
| #define | I2C_OAR1_OA1 ((uint32_t)0x000003FF) |
| #define | I2C_OAR1_OA1MODE ((uint32_t)0x00000400) |
| #define | I2C_OAR1_OA1EN ((uint32_t)0x00008000) |
| #define | I2C_OAR2_OA2 ((uint32_t)0x000000FE) |
| #define | I2C_OAR2_OA2MSK ((uint32_t)0x00000700) |
| #define | I2C_OAR2_OA2EN ((uint32_t)0x00008000) |
| #define | I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) |
| #define | I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) |
| #define | I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) |
| #define | I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) |
| #define | I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) |
| #define | I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) |
| #define | I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) |
| #define | I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) |
| #define | I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) |
| #define | I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) |
| #define | I2C_ISR_TXE ((uint32_t)0x00000001) |
| #define | I2C_ISR_TXIS ((uint32_t)0x00000002) |
| #define | I2C_ISR_RXNE ((uint32_t)0x00000004) |
| #define | I2C_ISR_ADDR ((uint32_t)0x00000008) |
| #define | I2C_ISR_NACKF ((uint32_t)0x00000010) |
| #define | I2C_ISR_STOPF ((uint32_t)0x00000020) |
| #define | I2C_ISR_TC ((uint32_t)0x00000040) |
| #define | I2C_ISR_TCR ((uint32_t)0x00000080) |
| #define | I2C_ISR_BERR ((uint32_t)0x00000100) |
| #define | I2C_ISR_ARLO ((uint32_t)0x00000200) |
| #define | I2C_ISR_OVR ((uint32_t)0x00000400) |
| #define | I2C_ISR_PECERR ((uint32_t)0x00000800) |
| #define | I2C_ISR_TIMEOUT ((uint32_t)0x00001000) |
| #define | I2C_ISR_ALERT ((uint32_t)0x00002000) |
| #define | I2C_ISR_BUSY ((uint32_t)0x00008000) |
| #define | I2C_ISR_DIR ((uint32_t)0x00010000) |
| #define | I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) |
| #define | I2C_ICR_ADDRCF ((uint32_t)0x00000008) |
| #define | I2C_ICR_NACKCF ((uint32_t)0x00000010) |
| #define | I2C_ICR_STOPCF ((uint32_t)0x00000020) |
| #define | I2C_ICR_BERRCF ((uint32_t)0x00000100) |
| #define | I2C_ICR_ARLOCF ((uint32_t)0x00000200) |
| #define | I2C_ICR_OVRCF ((uint32_t)0x00000400) |
| #define | I2C_ICR_PECCF ((uint32_t)0x00000800) |
| #define | I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) |
| #define | I2C_ICR_ALERTCF ((uint32_t)0x00002000) |
| #define | I2C_PECR_PEC ((uint32_t)0x000000FF) |
| #define | I2C_RXDR_RXDATA ((uint32_t)0x000000FF) |
| #define | I2C_TXDR_TXDATA ((uint32_t)0x000000FF) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | IWDG_SR_WVU ((uint8_t)0x04) |
| #define | IWDG_WINR_WIN ((uint16_t)0x0FFF) |
| #define | PWR_CR_LPSDSR ((uint16_t)0x0001) |
| #define | PWR_CR_PDDS ((uint16_t)0x0002) |
| #define | PWR_CR_CWUF ((uint16_t)0x0004) |
| #define | PWR_CR_CSBF ((uint16_t)0x0008) |
| #define | PWR_CR_PVDE ((uint16_t)0x0010) |
| #define | PWR_CR_PLS ((uint16_t)0x00E0) |
| #define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV0 ((uint16_t)0x0000) |
| #define | PWR_CR_PLS_LEV1 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_LEV2 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_LEV3 ((uint16_t)0x0060) |
| #define | PWR_CR_PLS_LEV4 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) |
| #define | PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) |
| #define | PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) |
| #define | PWR_CR_DBP ((uint16_t)0x0100) |
| #define | PWR_CSR_WUF ((uint16_t)0x0001) |
| #define | PWR_CSR_SBF ((uint16_t)0x0002) |
| #define | PWR_CSR_PVDO ((uint16_t)0x0004) |
| #define | PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) |
| #define | PWR_CSR_EWUP1 ((uint16_t)0x0100) |
| #define | PWR_CSR_EWUP2 ((uint16_t)0x0200) |
| #define | PWR_CSR_EWUP3 ((uint16_t)0x0400) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) |
| #define | RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) |
| #define | RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) |
| #define | RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) |
| #define | RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSICAL_0 ((uint32_t)0x00000100) |
| #define | RCC_CR_HSICAL_1 ((uint32_t)0x00000200) |
| #define | RCC_CR_HSICAL_2 ((uint32_t)0x00000400) |
| #define | RCC_CR_HSICAL_3 ((uint32_t)0x00000800) |
| #define | RCC_CR_HSICAL_4 ((uint32_t)0x00001000) |
| #define | RCC_CR_HSICAL_5 ((uint32_t)0x00002000) |
| #define | RCC_CR_HSICAL_6 ((uint32_t)0x00004000) |
| #define | RCC_CR_HSICAL_7 ((uint32_t)0x00008000) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCOF ((uint32_t)0x10000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) |
| #define | RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) |
| #define | RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) |
| #define | RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) |
| #define | RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) |
| #define | RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) |
| #define | RCC_AHBENR_TSEN ((uint32_t)0x01000000) |
| #define | RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) |
| #define | RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_LSEDRV ((uint32_t)0x00000018) |
| #define | RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) |
| #define | RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_OBLRSTF ((uint32_t)0x02000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) |
| #define | RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) |
| #define | RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) |
| #define | RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) |
| #define | RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) |
| #define | RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) |
| #define | RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) |
| #define | RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) |
| #define | RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) |
| #define | RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) |
| #define | RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) |
| #define | RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) |
| #define | RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) |
| #define | RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) |
| #define | RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) |
| #define | RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) |
| #define | RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) |
| #define | RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) |
| #define | RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) |
| #define | RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) |
| #define | RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) |
| #define | RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) |
| #define | RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) |
| #define | RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) |
| #define | RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) |
| #define | RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) |
| #define | RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) |
| #define | RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) |
| #define | RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) |
| #define | RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) |
| #define | RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) |
| #define | RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) |
| #define | RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) |
| #define | RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) |
| #define | RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) |
| #define | RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) |
| #define | RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) |
| #define | RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) |
| #define | RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) |
| #define | RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) |
| #define | RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) |
| #define | RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) |
| #define | RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) |
| #define | RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) |
| #define | RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) |
| #define | RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) |
| #define | RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) |
| #define | RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) |
| #define | RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) |
| #define | RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) |
| #define | RCC_CFGR3_USART1SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR3_I2CSW ((uint32_t)0x00000030) |
| #define | RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) |
| #define | RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) |
| #define | RCC_CFGR3_TIMSW ((uint32_t)0x00000300) |
| #define | RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) |
| #define | RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) |
| #define | RCC_CFGR3_USART2SW ((uint32_t)0x00030000) |
| #define | RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) |
| #define | RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) |
| #define | RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) |
| #define | RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR3_UART4SW ((uint32_t)0x00300000) |
| #define | RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) |
| #define | RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) |
| #define | RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) |
| #define | RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) |
| #define | RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_COSEL ((uint32_t)0x00080000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_WUTIE ((uint32_t)0x00004000) |
| #define | RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_WUTE ((uint32_t)0x00000400) |
| #define | RTC_CR_ALRBE ((uint32_t)0x00000200) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| #define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| #define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| #define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| #define | RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| #define | RTC_ISR_TAMP3F ((uint32_t)0x00008000) |
| #define | RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_WUTF ((uint32_t)0x00000400) |
| #define | RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_SHPF ((uint32_t)0x00000008) |
| #define | RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| #define | RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) |
| #define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| #define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_CALR_CALP ((uint32_t)0x00008000) |
| #define | RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| #define | RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| #define | RTC_CALR_CALM ((uint32_t)0x000001FF) |
| #define | RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| #define | RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| #define | RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| #define | RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| #define | RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| #define | RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| #define | RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| #define | RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| #define | RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| #define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| #define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| #define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| #define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| #define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| #define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| #define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| #define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| #define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| #define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| #define | RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) |
| #define | RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) |
| #define | RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) |
| #define | RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_CRCL ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint16_t)0x0001) |
| #define | SPI_CR2_TXDMAEN ((uint16_t)0x0002) |
| #define | SPI_CR2_SSOE ((uint16_t)0x0004) |
| #define | SPI_CR2_NSSP ((uint16_t)0x0008) |
| #define | SPI_CR2_FRF ((uint16_t)0x0010) |
| #define | SPI_CR2_ERRIE ((uint16_t)0x0020) |
| #define | SPI_CR2_RXNEIE ((uint16_t)0x0040) |
| #define | SPI_CR2_TXEIE ((uint16_t)0x0080) |
| #define | SPI_CR2_DS ((uint16_t)0x0F00) |
| #define | SPI_CR2_DS_0 ((uint16_t)0x0100) |
| #define | SPI_CR2_DS_1 ((uint16_t)0x0200) |
| #define | SPI_CR2_DS_2 ((uint16_t)0x0400) |
| #define | SPI_CR2_DS_3 ((uint16_t)0x0800) |
| #define | SPI_CR2_FRXTH ((uint16_t)0x1000) |
| #define | SPI_CR2_LDMARX ((uint16_t)0x2000) |
| #define | SPI_CR2_LDMATX ((uint16_t)0x4000) |
| #define | SPI_SR_RXNE ((uint16_t)0x0001) |
| #define | SPI_SR_TXE ((uint16_t)0x0002) |
| #define | SPI_SR_CRCERR ((uint16_t)0x0010) |
| #define | SPI_SR_MODF ((uint16_t)0x0020) |
| #define | SPI_SR_OVR ((uint16_t)0x0040) |
| #define | SPI_SR_BSY ((uint16_t)0x0080) |
| #define | SPI_SR_FRE ((uint16_t)0x0100) |
| #define | SPI_SR_FRLVL ((uint16_t)0x0600) |
| #define | SPI_SR_FRLVL_0 ((uint16_t)0x0200) |
| #define | SPI_SR_FRLVL_1 ((uint16_t)0x0400) |
| #define | SPI_SR_FTLVL ((uint16_t)0x1800) |
| #define | SPI_SR_FTLVL_0 ((uint16_t)0x0800) |
| #define | SPI_SR_FTLVL_1 ((uint16_t)0x1000) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) |
| #define | SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) |
| #define | SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) |
| #define | SYSCFG_CFGR1_DAC_TRIG_RMP ((uint32_t)0x00000080) |
| #define | SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) |
| #define | SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) |
| #define | SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) |
| #define | SYSCFG_CFGR1_TIM6DAC1_DMA_RMP ((uint32_t)0x00002000) |
| #define | SYSCFG_CFGR1_TIM7DAC2_DMA_RMP ((uint32_t)0x00004000) |
| #define | SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) |
| #define | SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) |
| #define | SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) |
| #define | SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) |
| #define | SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) |
| #define | SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) |
| #define | SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) |
| #define | SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) |
| #define | SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) |
| #define | SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) |
| #define | SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) |
| #define | SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) |
| #define | SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) |
| #define | SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) |
| #define | SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) |
| #define | SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) |
| #define | SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) |
| #define | SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) |
| #define | SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) |
| #define | SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) |
| #define | SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) |
| #define | SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) |
| #define | SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) |
| #define | SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration More... | |
| #define | SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration More... | |
| #define | SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration More... | |
| #define | SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration More... | |
| #define | SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) |
| #define | SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) |
| #define | SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) |
| #define | SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) |
| #define | SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR1_UIFREMAP ((uint16_t)0x0800) |
| #define | TIM_CR2_CCPC ((uint32_t)0x00000001) |
| #define | TIM_CR2_CCUS ((uint32_t)0x00000004) |
| #define | TIM_CR2_CCDS ((uint32_t)0x00000008) |
| #define | TIM_CR2_MMS ((uint32_t)0x00000070) |
| #define | TIM_CR2_MMS_0 ((uint32_t)0x00000010) |
| #define | TIM_CR2_MMS_1 ((uint32_t)0x00000020) |
| #define | TIM_CR2_MMS_2 ((uint32_t)0x00000040) |
| #define | TIM_CR2_TI1S ((uint32_t)0x00000080) |
| #define | TIM_CR2_OIS1 ((uint32_t)0x00000100) |
| #define | TIM_CR2_OIS1N ((uint32_t)0x00000200) |
| #define | TIM_CR2_OIS2 ((uint32_t)0x00000400) |
| #define | TIM_CR2_OIS2N ((uint32_t)0x00000800) |
| #define | TIM_CR2_OIS3 ((uint32_t)0x00001000) |
| #define | TIM_CR2_OIS3N ((uint32_t)0x00002000) |
| #define | TIM_CR2_OIS4 ((uint32_t)0x00004000) |
| #define | TIM_CR2_OIS5 ((uint32_t)0x00010000) |
| #define | TIM_CR2_OIS6 ((uint32_t)0x00020000) |
| #define | TIM_CR2_MMS2 ((uint32_t)0x00F00000) |
| #define | TIM_CR2_MMS2_0 ((uint32_t)0x00100000) |
| #define | TIM_CR2_MMS2_1 ((uint32_t)0x00200000) |
| #define | TIM_CR2_MMS2_2 ((uint32_t)0x00400000) |
| #define | TIM_CR2_MMS2_3 ((uint32_t)0x00800000) |
| #define | TIM_SMCR_SMS ((uint32_t)0x00010007) |
| #define | TIM_SMCR_SMS_0 ((uint32_t)0x00000001) |
| #define | TIM_SMCR_SMS_1 ((uint32_t)0x00000002) |
| #define | TIM_SMCR_SMS_2 ((uint32_t)0x00000004) |
| #define | TIM_SMCR_SMS_3 ((uint32_t)0x00010000) |
| #define | TIM_SMCR_OCCS ((uint32_t)0x00000008) |
| #define | TIM_SMCR_TS ((uint32_t)0x00000070) |
| #define | TIM_SMCR_TS_0 ((uint32_t)0x00000010) |
| #define | TIM_SMCR_TS_1 ((uint32_t)0x00000020) |
| #define | TIM_SMCR_TS_2 ((uint32_t)0x00000040) |
| #define | TIM_SMCR_MSM ((uint32_t)0x00000080) |
| #define | TIM_SMCR_ETF ((uint32_t)0x00000F00) |
| #define | TIM_SMCR_ETF_0 ((uint32_t)0x00000100) |
| #define | TIM_SMCR_ETF_1 ((uint32_t)0x00000200) |
| #define | TIM_SMCR_ETF_2 ((uint32_t)0x00000400) |
| #define | TIM_SMCR_ETF_3 ((uint32_t)0x00000800) |
| #define | TIM_SMCR_ETPS ((uint32_t)0x00003000) |
| #define | TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) |
| #define | TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) |
| #define | TIM_SMCR_ECE ((uint32_t)0x00004000) |
| #define | TIM_SMCR_ETP ((uint32_t)0x00008000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint32_t)0x00000001) |
| #define | TIM_SR_CC1IF ((uint32_t)0x00000002) |
| #define | TIM_SR_CC2IF ((uint32_t)0x00000004) |
| #define | TIM_SR_CC3IF ((uint32_t)0x00000008) |
| #define | TIM_SR_CC4IF ((uint32_t)0x00000010) |
| #define | TIM_SR_COMIF ((uint32_t)0x00000020) |
| #define | TIM_SR_TIF ((uint32_t)0x00000040) |
| #define | TIM_SR_BIF ((uint32_t)0x00000080) |
| #define | TIM_SR_B2IF ((uint32_t)0x00000100) |
| #define | TIM_SR_CC1OF ((uint32_t)0x00000200) |
| #define | TIM_SR_CC2OF ((uint32_t)0x00000400) |
| #define | TIM_SR_CC3OF ((uint32_t)0x00000800) |
| #define | TIM_SR_CC4OF ((uint32_t)0x00001000) |
| #define | TIM_SR_CC5IF ((uint32_t)0x00010000) |
| #define | TIM_SR_CC6IF ((uint32_t)0x00020000) |
| #define | TIM_EGR_UG ((uint16_t)0x0001) |
| #define | TIM_EGR_CC1G ((uint16_t)0x0002) |
| #define | TIM_EGR_CC2G ((uint16_t)0x0004) |
| #define | TIM_EGR_CC3G ((uint16_t)0x0008) |
| #define | TIM_EGR_CC4G ((uint16_t)0x0010) |
| #define | TIM_EGR_COMG ((uint16_t)0x0020) |
| #define | TIM_EGR_TG ((uint16_t)0x0040) |
| #define | TIM_EGR_BG ((uint16_t)0x0080) |
| #define | TIM_EGR_B2G ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC1S ((uint32_t)0x00000003) |
| #define | TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR1_OC1FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_OC1PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_OC1M ((uint32_t)0x00010070) |
| #define | TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) |
| #define | TIM_CCMR1_OC1CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_CC2S ((uint32_t)0x00000300) |
| #define | TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR1_OC2FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_OC2PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_OC2M ((uint32_t)0x01007000) |
| #define | TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) |
| #define | TIM_CCMR1_OC2CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) |
| #define | TIM_CCMR1_IC1F ((uint32_t)0x000000F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) |
| #define | TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) |
| #define | TIM_CCMR1_IC2F ((uint32_t)0x0000F000) |
| #define | TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_CC3S ((uint32_t)0x00000003) |
| #define | TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) |
| #define | TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) |
| #define | TIM_CCMR2_OC3FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR2_OC3PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR2_OC3M ((uint32_t)0x00000070) |
| #define | TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) |
| #define | TIM_CCMR2_OC3CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR2_CC4S ((uint32_t)0x00000300) |
| #define | TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) |
| #define | TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) |
| #define | TIM_CCMR2_OC4FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR2_OC4PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR2_OC4M ((uint32_t)0x00007000) |
| #define | TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) |
| #define | TIM_CCMR2_OC4CE ((uint32_t)0x00008000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x000000F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0x0000F000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) |
| #define | TIM_CCER_CC1E ((uint32_t)0x00000001) |
| #define | TIM_CCER_CC1P ((uint32_t)0x00000002) |
| #define | TIM_CCER_CC1NE ((uint32_t)0x00000004) |
| #define | TIM_CCER_CC1NP ((uint32_t)0x00000008) |
| #define | TIM_CCER_CC2E ((uint32_t)0x00000010) |
| #define | TIM_CCER_CC2P ((uint32_t)0x00000020) |
| #define | TIM_CCER_CC2NE ((uint32_t)0x00000040) |
| #define | TIM_CCER_CC2NP ((uint32_t)0x00000080) |
| #define | TIM_CCER_CC3E ((uint32_t)0x00000100) |
| #define | TIM_CCER_CC3P ((uint32_t)0x00000200) |
| #define | TIM_CCER_CC3NE ((uint32_t)0x00000400) |
| #define | TIM_CCER_CC3NP ((uint32_t)0x00000800) |
| #define | TIM_CCER_CC4E ((uint32_t)0x00001000) |
| #define | TIM_CCER_CC4P ((uint32_t)0x00002000) |
| #define | TIM_CCER_CC4NP ((uint32_t)0x00008000) |
| #define | TIM_CCER_CC5E ((uint32_t)0x00010000) |
| #define | TIM_CCER_CC5P ((uint32_t)0x00020000) |
| #define | TIM_CCER_CC6E ((uint32_t)0x00100000) |
| #define | TIM_CCER_CC6P ((uint32_t)0x00200000) |
| #define | TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) |
| #define | TIM_CNT_UIFCPY ((uint32_t)0x80000000) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) |
| #define | TIM_CCR5_GC5C1 ((uint32_t)0x20000000) |
| #define | TIM_CCR5_GC5C2 ((uint32_t)0x40000000) |
| #define | TIM_CCR5_GC5C3 ((uint32_t)0x80000000) |
| #define | TIM_CCR6_CCR6 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint32_t)0x000000FF) |
| #define | TIM_BDTR_DTG_0 ((uint32_t)0x00000001) |
| #define | TIM_BDTR_DTG_1 ((uint32_t)0x00000002) |
| #define | TIM_BDTR_DTG_2 ((uint32_t)0x00000004) |
| #define | TIM_BDTR_DTG_3 ((uint32_t)0x00000008) |
| #define | TIM_BDTR_DTG_4 ((uint32_t)0x00000010) |
| #define | TIM_BDTR_DTG_5 ((uint32_t)0x00000020) |
| #define | TIM_BDTR_DTG_6 ((uint32_t)0x00000040) |
| #define | TIM_BDTR_DTG_7 ((uint32_t)0x00000080) |
| #define | TIM_BDTR_LOCK ((uint32_t)0x00000300) |
| #define | TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) |
| #define | TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) |
| #define | TIM_BDTR_OSSI ((uint32_t)0x00000400) |
| #define | TIM_BDTR_OSSR ((uint32_t)0x00000800) |
| #define | TIM_BDTR_BKE ((uint32_t)0x00001000) |
| #define | TIM_BDTR_BKP ((uint32_t)0x00002000) |
| #define | TIM_BDTR_AOE ((uint32_t)0x00004000) |
| #define | TIM_BDTR_MOE ((uint32_t)0x00008000) |
| #define | TIM_BDTR_BKF ((uint32_t)0x000F0000) |
| #define | TIM_BDTR_BK2F ((uint32_t)0x00F00000) |
| #define | TIM_BDTR_BK2E ((uint32_t)0x01000000) |
| #define | TIM_BDTR_BK2P ((uint32_t)0x02000000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM16_OR_TI1_RMP ((uint16_t)0x00C0) |
| #define | TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) |
| #define | TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) |
| #define | TIM1_OR_ETR_RMP ((uint16_t)0x000F) |
| #define | TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) |
| #define | TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) |
| #define | TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) |
| #define | TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) |
| #define | TIM8_OR_ETR_RMP ((uint16_t)0x000F) |
| #define | TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) |
| #define | TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) |
| #define | TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) |
| #define | TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) |
| #define | TIM_CCMR3_OC5FE ((uint32_t)0x00000004) |
| #define | TIM_CCMR3_OC5PE ((uint32_t)0x00000008) |
| #define | TIM_CCMR3_OC5M ((uint32_t)0x00000070) |
| #define | TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) |
| #define | TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) |
| #define | TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) |
| #define | TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) |
| #define | TIM_CCMR3_OC5CE ((uint32_t)0x00000080) |
| #define | TIM_CCMR3_OC6FE ((uint32_t)0x00000400) |
| #define | TIM_CCMR3_OC6PE ((uint32_t)0x00000800) |
| #define | TIM_CCMR3_OC6M ((uint32_t)0x00007000) |
| #define | TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) |
| #define | TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) |
| #define | TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) |
| #define | TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) |
| #define | TIM_CCMR3_OC6CE ((uint32_t)0x00008000) |
| #define | USART_CR1_UE ((uint32_t)0x00000001) |
| #define | USART_CR1_UESM ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_MME ((uint32_t)0x00002000) |
| #define | USART_CR1_CMIE ((uint32_t)0x00004000) |
| #define | USART_CR1_OVER8 ((uint32_t)0x00008000) |
| #define | USART_CR1_DEDT ((uint32_t)0x001F0000) |
| #define | USART_CR1_DEDT_0 ((uint32_t)0x00010000) |
| #define | USART_CR1_DEDT_1 ((uint32_t)0x00020000) |
| #define | USART_CR1_DEDT_2 ((uint32_t)0x00040000) |
| #define | USART_CR1_DEDT_3 ((uint32_t)0x00080000) |
| #define | USART_CR1_DEDT_4 ((uint32_t)0x00100000) |
| #define | USART_CR1_DEAT ((uint32_t)0x03E00000) |
| #define | USART_CR1_DEAT_0 ((uint32_t)0x00200000) |
| #define | USART_CR1_DEAT_1 ((uint32_t)0x00400000) |
| #define | USART_CR1_DEAT_2 ((uint32_t)0x00800000) |
| #define | USART_CR1_DEAT_3 ((uint32_t)0x01000000) |
| #define | USART_CR1_DEAT_4 ((uint32_t)0x02000000) |
| #define | USART_CR1_RTOIE ((uint32_t)0x04000000) |
| #define | USART_CR1_EOBIE ((uint32_t)0x08000000) |
| #define | USART_CR2_ADDM7 ((uint32_t)0x00000010) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR2_SWAP ((uint32_t)0x00008000) |
| #define | USART_CR2_RXINV ((uint32_t)0x00010000) |
| #define | USART_CR2_TXINV ((uint32_t)0x00020000) |
| #define | USART_CR2_DATAINV ((uint32_t)0x00040000) |
| #define | USART_CR2_MSBFIRST ((uint32_t)0x00080000) |
| #define | USART_CR2_ABREN ((uint32_t)0x00100000) |
| #define | USART_CR2_ABRMODE ((uint32_t)0x00600000) |
| #define | USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) |
| #define | USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) |
| #define | USART_CR2_RTOEN ((uint32_t)0x00800000) |
| #define | USART_CR2_ADD ((uint32_t)0xFF000000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_CR3_ONEBIT ((uint32_t)0x00000800) |
| #define | USART_CR3_OVRDIS ((uint32_t)0x00001000) |
| #define | USART_CR3_DDRE ((uint32_t)0x00002000) |
| #define | USART_CR3_DEM ((uint32_t)0x00004000) |
| #define | USART_CR3_DEP ((uint32_t)0x00008000) |
| #define | USART_CR3_SCARCNT ((uint32_t)0x000E0000) |
| #define | USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) |
| #define | USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) |
| #define | USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) |
| #define | USART_CR3_WUS ((uint32_t)0x00300000) |
| #define | USART_CR3_WUS_0 ((uint32_t)0x00100000) |
| #define | USART_CR3_WUS_1 ((uint32_t)0x00200000) |
| #define | USART_CR3_WUFIE ((uint32_t)0x00400000) |
| #define | USART_BRR_DIV_FRACTION ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | USART_RTOR_RTO ((uint32_t)0x00FFFFFF) |
| #define | USART_RTOR_BLEN ((uint32_t)0xFF000000) |
| #define | USART_RQR_ABRRQ ((uint16_t)0x0001) |
| #define | USART_RQR_SBKRQ ((uint16_t)0x0002) |
| #define | USART_RQR_MMRQ ((uint16_t)0x0004) |
| #define | USART_RQR_RXFRQ ((uint16_t)0x0008) |
| #define | USART_RQR_TXFRQ ((uint16_t)0x0010) |
| #define | USART_ISR_PE ((uint32_t)0x00000001) |
| #define | USART_ISR_FE ((uint32_t)0x00000002) |
| #define | USART_ISR_NE ((uint32_t)0x00000004) |
| #define | USART_ISR_ORE ((uint32_t)0x00000008) |
| #define | USART_ISR_IDLE ((uint32_t)0x00000010) |
| #define | USART_ISR_RXNE ((uint32_t)0x00000020) |
| #define | USART_ISR_TC ((uint32_t)0x00000040) |
| #define | USART_ISR_TXE ((uint32_t)0x00000080) |
| #define | USART_ISR_LBD ((uint32_t)0x00000100) |
| #define | USART_ISR_CTSIF ((uint32_t)0x00000200) |
| #define | USART_ISR_CTS ((uint32_t)0x00000400) |
| #define | USART_ISR_RTOF ((uint32_t)0x00000800) |
| #define | USART_ISR_EOBF ((uint32_t)0x00001000) |
| #define | USART_ISR_ABRE ((uint32_t)0x00004000) |
| #define | USART_ISR_ABRF ((uint32_t)0x00008000) |
| #define | USART_ISR_BUSY ((uint32_t)0x00010000) |
| #define | USART_ISR_CMF ((uint32_t)0x00020000) |
| #define | USART_ISR_SBKF ((uint32_t)0x00040000) |
| #define | USART_ISR_RWU ((uint32_t)0x00080000) |
| #define | USART_ISR_WUF ((uint32_t)0x00100000) |
| #define | USART_ISR_TEACK ((uint32_t)0x00200000) |
| #define | USART_ISR_REACK ((uint32_t)0x00400000) |
| #define | USART_ICR_PECF ((uint32_t)0x00000001) |
| #define | USART_ICR_FECF ((uint32_t)0x00000002) |
| #define | USART_ICR_NCF ((uint32_t)0x00000004) |
| #define | USART_ICR_ORECF ((uint32_t)0x00000008) |
| #define | USART_ICR_IDLECF ((uint32_t)0x00000010) |
| #define | USART_ICR_TCCF ((uint32_t)0x00000040) |
| #define | USART_ICR_LBDCF ((uint32_t)0x00000100) |
| #define | USART_ICR_CTSCF ((uint32_t)0x00000200) |
| #define | USART_ICR_RTOCF ((uint32_t)0x00000800) |
| #define | USART_ICR_EOBCF ((uint32_t)0x00001000) |
| #define | USART_ICR_CMCF ((uint32_t)0x00020000) |
| #define | USART_ICR_WUCF ((uint32_t)0x00100000) |
| #define | USART_RDR_RDR ((uint16_t)0x01FF) |
| #define | USART_TDR_TDR ((uint16_t)0x01FF) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CAL ((uint32_t)0x00000004) |
| #define | ADC_CR2_RSTCAL ((uint32_t)0x00000008) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x00007000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) |
| #define | ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x000E0000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) |
| #define | ADC_CR2_EXTTRIG ((uint32_t)0x00100000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00200000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
| #define | ADC_HTR_HT ((uint16_t)0x0FFF) |
| #define | ADC_LTR_LT ((uint16_t)0x0FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | COMP_CSR_COMP1EN ((uint32_t)0x00000001) |
| #define | COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) |
| #define | COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) |
| #define | COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) |
| #define | COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) |
| #define | COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) |
| #define | COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) |
| #define | COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) |
| #define | COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) |
| #define | COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) |
| #define | COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) |
| #define | COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) |
| #define | COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) |
| #define | COMP_CSR_COMP1POL ((uint32_t)0x00000800) |
| #define | COMP_CSR_COMP1HYST ((uint32_t)0x00003000) |
| #define | COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) |
| #define | COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) |
| #define | COMP_CSR_COMP1OUT ((uint32_t)0x00004000) |
| #define | COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) |
| #define | COMP_CSR_COMP2EN ((uint32_t)0x00010000) |
| #define | COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) |
| #define | COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) |
| #define | COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) |
| #define | COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) |
| #define | COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) |
| #define | COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) |
| #define | COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) |
| #define | COMP_CSR_WNDWEN ((uint32_t)0x00800000) |
| #define | COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) |
| #define | COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) |
| #define | COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) |
| #define | COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) |
| #define | COMP_CSR_COMP2POL ((uint32_t)0x08000000) |
| #define | COMP_CSR_COMP2HYST ((uint32_t)0x30000000) |
| #define | COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) |
| #define | COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) |
| #define | COMP_CSR_COMP2OUT ((uint32_t)0x40000000) |
| #define | COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) |
| #define | CAN_MCR_INRQ ((uint16_t)0x0001) |
| #define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
| #define | CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define | CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define | CAN_MCR_NART ((uint16_t)0x0010) |
| #define | CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define | CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define | CAN_MCR_TTCM ((uint16_t)0x0080) |
| #define | CAN_MCR_RESET ((uint16_t)0x8000) |
| #define | CAN_MSR_INAK ((uint16_t)0x0001) |
| #define | CAN_MSR_SLAK ((uint16_t)0x0002) |
| #define | CAN_MSR_ERRI ((uint16_t)0x0004) |
| #define | CAN_MSR_WKUI ((uint16_t)0x0008) |
| #define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
| #define | CAN_MSR_TXM ((uint16_t)0x0100) |
| #define | CAN_MSR_RXM ((uint16_t)0x0200) |
| #define | CAN_MSR_SAMP ((uint16_t)0x0400) |
| #define | CAN_MSR_RX ((uint16_t)0x0800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
| #define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
| #define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
| #define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
| #define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
| #define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
| #define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
| #define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint8_t)0x01) |
| #define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
| #define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
| #define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
| #define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
| #define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
| #define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
| #define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
| #define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
| #define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
| #define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
| #define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
| #define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
| #define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
| #define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
| #define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
| #define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
| #define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
| #define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
| #define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
| #define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
| #define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
| #define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
| #define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
| #define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
| #define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
| #define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
| #define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
| #define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
| #define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
| #define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
| #define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
| #define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
| #define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
| #define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
| #define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
| #define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
| #define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
| #define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
| #define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
| #define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
| #define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
| #define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
| #define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
| #define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
| #define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
| #define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
| #define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
| #define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
| #define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
| #define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
| #define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
| #define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
| #define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
| #define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
| #define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
| #define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
| #define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
| #define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
| #define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
| #define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | CRC_CR_POLSIZE ((uint32_t)0x00000018) |
| #define | CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) |
| #define | CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) |
| #define | CRC_CR_REV_IN ((uint32_t)0x00000060) |
| #define | CRC_CR_REV_IN_0 ((uint32_t)0x00000020) |
| #define | CRC_CR_REV_IN_1 ((uint32_t)0x00000040) |
| #define | CRC_CR_REV_OUT ((uint32_t)0x00000080) |
| #define | CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) |
| #define | CRC_POL_POL ((uint32_t)0xFFFFFFFF) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| #define | DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
| #define | DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_APB1_FZ_DBG_TIM18_STOP ((uint32_t)0x00000200) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB2_FZ_DBG_TIM19_STOP ((uint32_t)0x00000020) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR_EN ((uint32_t)0x00000001) |
| #define | DMA_CCR_TCIE ((uint32_t)0x00000002) |
| #define | DMA_CCR_HTIE ((uint32_t)0x00000004) |
| #define | DMA_CCR_TEIE ((uint32_t)0x00000008) |
| #define | DMA_CCR_DIR ((uint32_t)0x00000010) |
| #define | DMA_CCR_CIRC ((uint32_t)0x00000020) |
| #define | DMA_CCR_PINC ((uint32_t)0x00000040) |
| #define | DMA_CCR_MINC ((uint32_t)0x00000080) |
| #define | DMA_CCR_PSIZE ((uint32_t)0x00000300) |
| #define | DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | DMA_CCR_MSIZE ((uint32_t)0x00000C00) |
| #define | DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) |
| #define | DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) |
| #define | DMA_CCR_PL ((uint32_t)0x00003000) |
| #define | DMA_CCR_PL_0 ((uint32_t)0x00001000) |
| #define | DMA_CCR_PL_1 ((uint32_t)0x00002000) |
| #define | DMA_CCR_MEM2MEM ((uint32_t)0x00004000) |
| #define | DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) |
| #define | DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_IMR_MR20 ((uint32_t)0x00100000) |
| #define | EXTI_IMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_IMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_IMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_IMR_MR24 ((uint32_t)0x01000000) |
| #define | EXTI_IMR_MR25 ((uint32_t)0x02000000) |
| #define | EXTI_IMR_MR26 ((uint32_t)0x04000000) |
| #define | EXTI_IMR_MR27 ((uint32_t)0x08000000) |
| #define | EXTI_IMR_MR28 ((uint32_t)0x10000000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR20 ((uint32_t)0x00100000) |
| #define | EXTI_EMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_EMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_EMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_EMR_MR24 ((uint32_t)0x01000000) |
| #define | EXTI_EMR_MR25 ((uint32_t)0x02000000) |
| #define | EXTI_EMR_MR26 ((uint32_t)0x04000000) |
| #define | EXTI_EMR_MR27 ((uint32_t)0x08000000) |
| #define | EXTI_EMR_MR28 ((uint32_t)0x10000000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR20 ((uint32_t)0x00100000) |
| #define | EXTI_RTSR_TR21 ((uint32_t)0x00200000) |
| #define | EXTI_RTSR_TR22 ((uint32_t)0x00400000) |
| #define | EXTI_RTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_RTSR_TR24 ((uint32_t)0x01000000) |
| #define | EXTI_RTSR_TR25 ((uint32_t)0x02000000) |
| #define | EXTI_RTSR_TR26 ((uint32_t)0x04000000) |
| #define | EXTI_RTSR_TR27 ((uint32_t)0x08000000) |
| #define | EXTI_RTSR_TR28 ((uint32_t)0x10000000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR20 ((uint32_t)0x00100000) |
| #define | EXTI_FTSR_TR21 ((uint32_t)0x00200000) |
| #define | EXTI_FTSR_TR22 ((uint32_t)0x00400000) |
| #define | EXTI_FTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_FTSR_TR24 ((uint32_t)0x01000000) |
| #define | EXTI_FTSR_TR25 ((uint32_t)0x02000000) |
| #define | EXTI_FTSR_TR26 ((uint32_t)0x04000000) |
| #define | EXTI_FTSR_TR27 ((uint32_t)0x08000000) |
| #define | EXTI_FTSR_TR28 ((uint32_t)0x10000000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) |
| #define | EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) |
| #define | EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) |
| #define | EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) |
| #define | EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) |
| #define | EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) |
| #define | EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) |
| #define | EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) |
| #define | EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR20 ((uint32_t)0x00100000) |
| #define | EXTI_PR_PR21 ((uint32_t)0x00200000) |
| #define | EXTI_PR_PR22 ((uint32_t)0x00400000) |
| #define | EXTI_PR_PR23 ((uint32_t)0x00800000) |
| #define | EXTI_PR_PR24 ((uint32_t)0x01000000) |
| #define | EXTI_PR_PR25 ((uint32_t)0x02000000) |
| #define | EXTI_PR_PR26 ((uint32_t)0x04000000) |
| #define | EXTI_PR_PR27 ((uint32_t)0x08000000) |
| #define | EXTI_PR_PR28 ((uint32_t)0x10000000) |
| #define | FLASH_ACR_LATENCY ((uint8_t)0x03) |
| #define | FLASH_ACR_LATENCY_0 ((uint8_t)0x01) |
| #define | FLASH_ACR_LATENCY_1 ((uint8_t)0x02) |
| #define | FLASH_ACR_HLFCYA ((uint8_t)0x08) |
| #define | FLASH_ACR_PRFTBE ((uint8_t)0x10) |
| #define | FLASH_ACR_PRFTBS ((uint8_t)0x20) |
| #define | FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_PGERR ((uint32_t)0x00000004) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000020) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_PER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_OPTPG ((uint32_t)0x00000010) |
| #define | FLASH_CR_OPTER ((uint32_t)0x00000020) |
| #define | FLASH_CR_STRT ((uint32_t)0x00000040) |
| #define | FLASH_CR_LOCK ((uint32_t)0x00000080) |
| #define | FLASH_CR_OPTWRE ((uint32_t)0x00000200) |
| #define | FLASH_CR_ERRIE ((uint32_t)0x00000400) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x00001000) |
| #define | FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) |
| #define | FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OBR_OPTERR ((uint32_t)0x00000001) |
| #define | FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) |
| #define | FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) |
| #define | FLASH_OBR_USER ((uint32_t)0x00003700) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | OB_RDP_RDP ((uint32_t)0x000000FF) |
| #define | OB_RDP_nRDP ((uint32_t)0x0000FF00) |
| #define | OB_USER_USER ((uint32_t)0x00FF0000) |
| #define | OB_USER_nUSER ((uint32_t)0xFF000000) |
| #define | OB_WRP0_WRP0 ((uint32_t)0x000000FF) |
| #define | OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) |
| #define | OB_WRP1_WRP1 ((uint32_t)0x00FF0000) |
| #define | OB_WRP1_nWRP1 ((uint32_t)0xFF000000) |
| #define | OB_WRP2_WRP2 ((uint32_t)0x000000FF) |
| #define | OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) |
| #define | OB_WRP3_WRP3 ((uint32_t)0x00FF0000) |
| #define | OB_WRP3_nWRP3 ((uint32_t)0xFF000000) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) |
| #define | GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) |
| #define | GPIO_BRR_BR_0 ((uint32_t)0x00000001) |
| #define | GPIO_BRR_BR_1 ((uint32_t)0x00000002) |
| #define | GPIO_BRR_BR_2 ((uint32_t)0x00000004) |
| #define | GPIO_BRR_BR_3 ((uint32_t)0x00000008) |
| #define | GPIO_BRR_BR_4 ((uint32_t)0x00000010) |
| #define | GPIO_BRR_BR_5 ((uint32_t)0x00000020) |
| #define | GPIO_BRR_BR_6 ((uint32_t)0x00000040) |
| #define | GPIO_BRR_BR_7 ((uint32_t)0x00000080) |
| #define | GPIO_BRR_BR_8 ((uint32_t)0x00000100) |
| #define | GPIO_BRR_BR_9 ((uint32_t)0x00000200) |
| #define | GPIO_BRR_BR_10 ((uint32_t)0x00000400) |
| #define | GPIO_BRR_BR_11 ((uint32_t)0x00000800) |
| #define | GPIO_BRR_BR_12 ((uint32_t)0x00001000) |
| #define | GPIO_BRR_BR_13 ((uint32_t)0x00002000) |
| #define | GPIO_BRR_BR_14 ((uint32_t)0x00004000) |
| #define | GPIO_BRR_BR_15 ((uint32_t)0x00008000) |
| #define | I2C_CR1_PE ((uint32_t)0x00000001) |
| #define | I2C_CR1_TXIE ((uint32_t)0x00000002) |
| #define | I2C_CR1_RXIE ((uint32_t)0x00000004) |
| #define | I2C_CR1_ADDRIE ((uint32_t)0x00000008) |
| #define | I2C_CR1_NACKIE ((uint32_t)0x00000010) |
| #define | I2C_CR1_STOPIE ((uint32_t)0x00000020) |
| #define | I2C_CR1_TCIE ((uint32_t)0x00000040) |
| #define | I2C_CR1_ERRIE ((uint32_t)0x00000080) |
| #define | I2C_CR1_DFN ((uint32_t)0x00000F00) |
| #define | I2C_CR1_ANFOFF ((uint32_t)0x00001000) |
| #define | I2C_CR1_SWRST ((uint32_t)0x00002000) |
| #define | I2C_CR1_TXDMAEN ((uint32_t)0x00004000) |
| #define | I2C_CR1_RXDMAEN ((uint32_t)0x00008000) |
| #define | I2C_CR1_SBC ((uint32_t)0x00010000) |
| #define | I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) |
| #define | I2C_CR1_WUPEN ((uint32_t)0x00040000) |
| #define | I2C_CR1_GCEN ((uint32_t)0x00080000) |
| #define | I2C_CR1_SMBHEN ((uint32_t)0x00100000) |
| #define | I2C_CR1_SMBDEN ((uint32_t)0x00200000) |
| #define | I2C_CR1_ALERTEN ((uint32_t)0x00400000) |
| #define | I2C_CR1_PECEN ((uint32_t)0x00800000) |
| #define | I2C_CR2_SADD ((uint32_t)0x000003FF) |
| #define | I2C_CR2_RD_WRN ((uint32_t)0x00000400) |
| #define | I2C_CR2_ADD10 ((uint32_t)0x00000800) |
| #define | I2C_CR2_HEAD10R ((uint32_t)0x00001000) |
| #define | I2C_CR2_START ((uint32_t)0x00002000) |
| #define | I2C_CR2_STOP ((uint32_t)0x00004000) |
| #define | I2C_CR2_NACK ((uint32_t)0x00008000) |
| #define | I2C_CR2_NBYTES ((uint32_t)0x00FF0000) |
| #define | I2C_CR2_RELOAD ((uint32_t)0x01000000) |
| #define | I2C_CR2_AUTOEND ((uint32_t)0x02000000) |
| #define | I2C_CR2_PECBYTE ((uint32_t)0x04000000) |
| #define | I2C_OAR1_OA1 ((uint32_t)0x000003FF) |
| #define | I2C_OAR1_OA1MODE ((uint32_t)0x00000400) |
| #define | I2C_OAR1_OA1EN ((uint32_t)0x00008000) |
| #define | I2C_OAR2_OA2 ((uint32_t)0x000000FE) |
| #define | I2C_OAR2_OA2MSK ((uint32_t)0x00000700) |
| #define | I2C_OAR2_OA2EN ((uint32_t)0x00008000) |
| #define | I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) |
| #define | I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) |
| #define | I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) |
| #define | I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) |
| #define | I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) |
| #define | I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) |
| #define | I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) |
| #define | I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) |
| #define | I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) |
| #define | I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) |
| #define | I2C_ISR_TXE ((uint32_t)0x00000001) |
| #define | I2C_ISR_TXIS ((uint32_t)0x00000002) |
| #define | I2C_ISR_RXNE ((uint32_t)0x00000004) |
| #define | I2C_ISR_ADDR ((uint32_t)0x00000008) |
| #define | I2C_ISR_NACKF ((uint32_t)0x00000010) |
| #define | I2C_ISR_STOPF ((uint32_t)0x00000020) |
| #define | I2C_ISR_TC ((uint32_t)0x00000040) |
| #define | I2C_ISR_TCR ((uint32_t)0x00000080) |
| #define | I2C_ISR_BERR ((uint32_t)0x00000100) |
| #define | I2C_ISR_ARLO ((uint32_t)0x00000200) |
| #define | I2C_ISR_OVR ((uint32_t)0x00000400) |
| #define | I2C_ISR_PECERR ((uint32_t)0x00000800) |
| #define | I2C_ISR_TIMEOUT ((uint32_t)0x00001000) |
| #define | I2C_ISR_ALERT ((uint32_t)0x00002000) |
| #define | I2C_ISR_BUSY ((uint32_t)0x00008000) |
| #define | I2C_ISR_DIR ((uint32_t)0x00010000) |
| #define | I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) |
| #define | I2C_ICR_ADDRCF ((uint32_t)0x00000008) |
| #define | I2C_ICR_NACKCF ((uint32_t)0x00000010) |
| #define | I2C_ICR_STOPCF ((uint32_t)0x00000020) |
| #define | I2C_ICR_BERRCF ((uint32_t)0x00000100) |
| #define | I2C_ICR_ARLOCF ((uint32_t)0x00000200) |
| #define | I2C_ICR_OVRCF ((uint32_t)0x00000400) |
| #define | I2C_ICR_PECCF ((uint32_t)0x00000800) |
| #define | I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) |
| #define | I2C_ICR_ALERTCF ((uint32_t)0x00002000) |
| #define | I2C_PECR_PEC ((uint32_t)0x000000FF) |
| #define | I2C_RXDR_RXDATA ((uint32_t)0x000000FF) |
| #define | I2C_TXDR_TXDATA ((uint32_t)0x000000FF) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | IWDG_SR_WVU ((uint8_t)0x04) |
| #define | IWDG_WINR_WIN ((uint16_t)0x0FFF) |
| #define | CEC_CR_CECEN ((uint32_t)0x00000001) |
| #define | CEC_CR_TXSOM ((uint32_t)0x00000002) |
| #define | CEC_CR_TXEOM ((uint32_t)0x00000004) |
| #define | CEC_CFGR_SFT ((uint32_t)0x00000007) |
| #define | CEC_CFGR_RXTOL ((uint32_t)0x00000008) |
| #define | CEC_CFGR_BRESTP ((uint32_t)0x00000010) |
| #define | CEC_CFGR_BREGEN ((uint32_t)0x00000020) |
| #define | CEC_CFGR_LREGEN ((uint32_t)0x00000040) |
| #define | CEC_CFGR_SFTOPT ((uint32_t)0x00000100) |
| #define | CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) |
| #define | CEC_CFGR_OAR ((uint32_t)0x7FFF0000) |
| #define | CEC_CFGR_LSTN ((uint32_t)0x80000000) |
| #define | CEC_TXDR_TXD ((uint32_t)0x000000FF) |
| #define | CEC_TXDR_RXD ((uint32_t)0x000000FF) |
| #define | CEC_ISR_RXBR ((uint32_t)0x00000001) |
| #define | CEC_ISR_RXEND ((uint32_t)0x00000002) |
| #define | CEC_ISR_RXOVR ((uint32_t)0x00000004) |
| #define | CEC_ISR_BRE ((uint32_t)0x00000008) |
| #define | CEC_ISR_SBPE ((uint32_t)0x00000010) |
| #define | CEC_ISR_LBPE ((uint32_t)0x00000020) |
| #define | CEC_ISR_RXACKE ((uint32_t)0x00000040) |
| #define | CEC_ISR_ARBLST ((uint32_t)0x00000080) |
| #define | CEC_ISR_TXBR ((uint32_t)0x00000100) |
| #define | CEC_ISR_TXEND ((uint32_t)0x00000200) |
| #define | CEC_ISR_TXUDR ((uint32_t)0x00000400) |
| #define | CEC_ISR_TXERR ((uint32_t)0x00000800) |
| #define | CEC_ISR_TXACKE ((uint32_t)0x00001000) |
| #define | CEC_IER_RXBRIE ((uint32_t)0x00000001) |
| #define | CEC_IER_RXENDIE ((uint32_t)0x00000002) |
| #define | CEC_IER_RXOVRIE ((uint32_t)0x00000004) |
| #define | CEC_IER_BREIEIE ((uint32_t)0x00000008) |
| #define | CEC_IER_SBPEIE ((uint32_t)0x00000010) |
| #define | CEC_IER_LBPEIE ((uint32_t)0x00000020) |
| #define | CEC_IER_RXACKEIE ((uint32_t)0x00000040) |
| #define | CEC_IER_ARBLSTIE ((uint32_t)0x00000080) |
| #define | CEC_IER_TXBRIE ((uint32_t)0x00000100) |
| #define | CEC_IER_TXENDIE ((uint32_t)0x00000200) |
| #define | CEC_IER_TXUDRIE ((uint32_t)0x00000400) |
| #define | CEC_IER_TXERRIE ((uint32_t)0x00000800) |
| #define | CEC_IER_TXACKEIE ((uint32_t)0x00001000) |
| #define | PWR_CR_LPSDSR ((uint16_t)0x0001) |
| #define | PWR_CR_PDDS ((uint16_t)0x0002) |
| #define | PWR_CR_CWUF ((uint16_t)0x0004) |
| #define | PWR_CR_CSBF ((uint16_t)0x0008) |
| #define | PWR_CR_PVDE ((uint16_t)0x0010) |
| #define | PWR_CR_PLS ((uint16_t)0x00E0) |
| #define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV0 ((uint16_t)0x0000) |
| #define | PWR_CR_PLS_LEV1 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_LEV2 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_LEV3 ((uint16_t)0x0060) |
| #define | PWR_CR_PLS_LEV4 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) |
| #define | PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) |
| #define | PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) |
| #define | PWR_CR_DBP ((uint16_t)0x0100) |
| #define | PWR_CR_SDADC1EN ((uint16_t)0x0200) |
| #define | PWR_CR_SDADC2EN ((uint16_t)0x0400) |
| #define | PWR_CR_SDADC3EN ((uint16_t)0x0800) |
| #define | PWR_CSR_WUF ((uint16_t)0x0001) |
| #define | PWR_CSR_SBF ((uint16_t)0x0002) |
| #define | PWR_CSR_PVDO ((uint16_t)0x0004) |
| #define | PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) |
| #define | PWR_CSR_EWUP1 ((uint16_t)0x0100) |
| #define | PWR_CSR_EWUP2 ((uint16_t)0x0200) |
| #define | PWR_CSR_EWUP3 ((uint16_t)0x0400) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) |
| #define | RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) |
| #define | RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) |
| #define | RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) |
| #define | RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSICAL_0 ((uint32_t)0x00000100) |
| #define | RCC_CR_HSICAL_1 ((uint32_t)0x00000200) |
| #define | RCC_CR_HSICAL_2 ((uint32_t)0x00000400) |
| #define | RCC_CR_HSICAL_3 ((uint32_t)0x00000800) |
| #define | RCC_CR_HSICAL_4 ((uint32_t)0x00001000) |
| #define | RCC_CR_HSICAL_5 ((uint32_t)0x00002000) |
| #define | RCC_CR_HSICAL_6 ((uint32_t)0x00004000) |
| #define | RCC_CR_HSICAL_7 ((uint32_t)0x00008000) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) |
| #define | RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) |
| #define | RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) |
| #define | RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) |
| #define | RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) |
| #define | RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) |
| #define | RCC_CFGR_USBPRE ((uint32_t)0x00400000) |
| #define | RCC_CFGR_MCO ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) |
| #define | RCC_CFGR_SDADCPRE ((uint32_t)0xF8000000) |
| #define | RCC_CFGR_SDADCPRE_0 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_SDADCPRE_1 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_SDADCPRE_2 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_SDADCPRE_3 ((uint32_t)0x40000000) |
| #define | RCC_CFGR_SDADCPRE_4 ((uint32_t)0x80000000) |
| #define | RCC_CFGR_SDADCPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SDADCPRE_DIV2 ((uint32_t)0x80000000) |
| #define | RCC_CFGR_SDADCPRE_DIV4 ((uint32_t)0x88000000) |
| #define | RCC_CFGR_SDADCPRE_DIV6 ((uint32_t)0x90000000) |
| #define | RCC_CFGR_SDADCPRE_DIV8 ((uint32_t)0x98000000) |
| #define | RCC_CFGR_SDADCPRE_DIV10 ((uint32_t)0xA0000000) |
| #define | RCC_CFGR_SDADCPRE_DIV12 ((uint32_t)0xA8000000) |
| #define | RCC_CFGR_SDADCPRE_DIV14 ((uint32_t)0xB0000000) |
| #define | RCC_CFGR_SDADCPRE_DIV16 ((uint32_t)0xB8000000) |
| #define | RCC_CFGR_SDADCPRE_DIV20 ((uint32_t)0xC0000000) |
| #define | RCC_CFGR_SDADCPRE_DIV24 ((uint32_t)0xC8000000) |
| #define | RCC_CFGR_SDADCPRE_DIV28 ((uint32_t)0xD0000000) |
| #define | RCC_CFGR_SDADCPRE_DIV32 ((uint32_t)0xD8000000) |
| #define | RCC_CFGR_SDADCPRE_DIV36 ((uint32_t)0xE0000000) |
| #define | RCC_CFGR_SDADCPRE_DIV40 ((uint32_t)0xE8000000) |
| #define | RCC_CFGR_SDADCPRE_DIV44 ((uint32_t)0xF0000000) |
| #define | RCC_CFGR_SDADCPRE_DIV48 ((uint32_t)0xF8000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) |
| #define | RCC_APB2RSTR_TIM19RST ((uint32_t)0x00080000) |
| #define | RCC_APB2RSTR_SDADC1RST ((uint32_t)0x01000000) |
| #define | RCC_APB2RSTR_SDADC2RST ((uint32_t)0x02000000) |
| #define | RCC_APB2RSTR_SDADC3RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_TIM18RST ((uint32_t)0x00000200) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) |
| #define | RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) |
| #define | RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) |
| #define | RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) |
| #define | RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) |
| #define | RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) |
| #define | RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) |
| #define | RCC_AHBENR_TSEN ((uint32_t)0x01000000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_TIM19EN ((uint32_t)0x00080000) |
| #define | RCC_APB2ENR_SDADC1EN ((uint32_t)0x01000000) |
| #define | RCC_APB2ENR_SDADC2EN ((uint32_t)0x02000000) |
| #define | RCC_APB2ENR_SDADC3EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_TIM18EN ((uint32_t)0x00000200) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) |
| #define | RCC_APB1ENR_CECEN ((uint32_t)0x40000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_LSEDRV ((uint32_t)0x00000018) |
| #define | RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) |
| #define | RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_OBL ((uint32_t)0x02000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) |
| #define | RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) |
| #define | RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) |
| #define | RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) |
| #define | RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) |
| #define | RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) |
| #define | RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) |
| #define | RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) |
| #define | RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) |
| #define | RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) |
| #define | RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) |
| #define | RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) |
| #define | RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) |
| #define | RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) |
| #define | RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) |
| #define | RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) |
| #define | RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) |
| #define | RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) |
| #define | RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) |
| #define | RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) |
| #define | RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) |
| #define | RCC_CFGR3_USART1SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR3_I2CSW ((uint32_t)0x00000030) |
| #define | RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) |
| #define | RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) |
| #define | RCC_CFGR3_CECSW ((uint32_t)0x00000040) |
| #define | RCC_CFGR3_USART2SW ((uint32_t)0x00030000) |
| #define | RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) |
| #define | RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) |
| #define | RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) |
| #define | RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_COSEL ((uint32_t)0x00080000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_WUTIE ((uint32_t)0x00004000) |
| #define | RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_WUTE ((uint32_t)0x00000400) |
| #define | RTC_CR_ALRBE ((uint32_t)0x00000200) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| #define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| #define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| #define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| #define | RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| #define | RTC_ISR_TAMP3F ((uint32_t)0x00008000) |
| #define | RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_WUTF ((uint32_t)0x00000400) |
| #define | RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_SHPF ((uint32_t)0x00000008) |
| #define | RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| #define | RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) |
| #define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| #define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_CALR_CALP ((uint32_t)0x00008000) |
| #define | RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| #define | RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| #define | RTC_CALR_CALM ((uint32_t)0x000001FF) |
| #define | RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| #define | RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| #define | RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| #define | RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| #define | RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| #define | RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| #define | RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| #define | RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| #define | RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| #define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| #define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| #define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| #define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| #define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| #define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| #define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| #define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| #define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| #define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| #define | RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) |
| #define | RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) |
| #define | RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) |
| #define | RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP20R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP21R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP22R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP23R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP24R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP25R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP26R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP27R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP28R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP29R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP30R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP31R ((uint32_t)0xFFFFFFFF) |
| #define | SDADC_CR1_EOCALIE ((uint32_t)0x00000001) |
| #define | SDADC_CR1_JEOCIE ((uint32_t)0x00000002) |
| #define | SDADC_CR1_JOVRIE ((uint32_t)0x00000004) |
| #define | SDADC_CR1_REOCIE ((uint32_t)0x00000008) |
| #define | SDADC_CR1_ROVRIE ((uint32_t)0x00000010) |
| #define | SDADC_CR1_REFV ((uint32_t)0x00000300) |
| #define | SDADC_CR1_REFV_0 ((uint32_t)0x00000100) |
| #define | SDADC_CR1_REFV_1 ((uint32_t)0x00000200) |
| #define | SDADC_CR1_SLOWCK ((uint32_t)0x00000400) |
| #define | SDADC_CR1_SBI ((uint32_t)0x00000800) |
| #define | SDADC_CR1_PDI ((uint32_t)0x00001000) |
| #define | SDADC_CR1_JSYNC ((uint32_t)0x00004000) |
| #define | SDADC_CR1_RSYNC ((uint32_t)0x00008000) |
| #define | SDADC_CR1_JDMAEN ((uint32_t)0x00010000) |
| #define | SDADC_CR1_RDMAEN ((uint32_t)0x00020000) |
| #define | SDADC_CR1_INIT ((uint32_t)0x80000000) |
| #define | SDADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | SDADC_CR2_CALIBCNT ((uint32_t)0x00000006) |
| #define | SDADC_CR2_CALIBCNT_0 ((uint32_t)0x00000002) |
| #define | SDADC_CR2_CALIBCNT_1 ((uint32_t)0x00000004) |
| #define | SDADC_CR2_STARTCALIB ((uint32_t)0x00000010) |
| #define | SDADC_CR2_JCONT ((uint32_t)0x00000020) |
| #define | SDADC_CR2_JDS ((uint32_t)0x00000040) |
| #define | SDADC_CR2_JEXTSEL ((uint32_t)0x00000F00) |
| #define | SDADC_CR2_JEXTSEL_0 ((uint32_t)0x00000100) |
| #define | SDADC_CR2_JEXTSEL_1 ((uint32_t)0x00000200) |
| #define | SDADC_CR2_JEXTSEL_2 ((uint32_t)0x00000400) |
| #define | SDADC_CR2_JEXTSEL_3 ((uint32_t)0x00000800) |
| #define | SDADC_CR2_JEXTEN ((uint32_t)0x00006000) |
| #define | SDADC_CR2_JEXTEN_0 ((uint32_t)0x00002000) |
| #define | SDADC_CR2_JEXTEN_1 ((uint32_t)0x00004000) |
| #define | SDADC_CR2_JSWSTART ((uint32_t)0x00008000) |
| #define | SDADC_CR2_RCH ((uint32_t)0x000F0000) |
| #define | SDADC_CR2_RCH_0 ((uint32_t)0x00010000) |
| #define | SDADC_CR2_RCH_1 ((uint32_t)0x00020000) |
| #define | SDADC_CR2_RCH_2 ((uint32_t)0x00040000) |
| #define | SDADC_CR2_RCH_3 ((uint32_t)0x00080000) |
| #define | SDADC_CR2_RCONT ((uint32_t)0x00400000) |
| #define | SDADC_CR2_RSWSTART ((uint32_t)0x00800000) |
| #define | SDADC_CR2_FAST ((uint32_t)0x01000000) |
| #define | SDADC_ISR_EOCALF ((uint32_t)0x00000001) |
| #define | SDADC_ISR_JEOCF ((uint32_t)0x00000002) |
| #define | SDADC_ISR_JOVRF ((uint32_t)0x00000004) |
| #define | SDADC_ISR_REOCF ((uint32_t)0x00000010) |
| #define | SDADC_ISR_ROVRF ((uint32_t)0x00000020) |
| #define | SDADC_ISR_CALIBIP ((uint32_t)0x00001000) |
| #define | SDADC_ISR_JCIP ((uint32_t)0x00002000) |
| #define | SDADC_ISR_RCIP ((uint32_t)0x00004000) |
| #define | SDADC_ISR_STABIP ((uint32_t)0x00008000) |
| #define | SDADC_ISR_INITRDY ((uint32_t)0x80000000) |
| #define | SDADC_ISR_CLREOCALF ((uint32_t)0x00000001) |
| #define | SDADC_ISR_CLRJOVRF ((uint32_t)0x00000004) |
| #define | SDADC_ISR_CLRROVRF ((uint32_t)0x00000010) |
| #define | SDADC_JCHGR_JCHG ((uint32_t)0x000001FF) |
| #define | SDADC_JCHGR_JCHG_0 ((uint32_t)0x00000001) |
| #define | SDADC_JCHGR_JCHG_1 ((uint32_t)0x00000002) |
| #define | SDADC_JCHGR_JCHG_2 ((uint32_t)0x00000004) |
| #define | SDADC_JCHGR_JCHG_3 ((uint32_t)0x00000008) |
| #define | SDADC_JCHGR_JCHG_4 ((uint32_t)0x00000010) |
| #define | SDADC_JCHGR_JCHG_5 ((uint32_t)0x00000020) |
| #define | SDADC_JCHGR_JCHG_6 ((uint32_t)0x00000040) |
| #define | SDADC_JCHGR_JCHG_7 ((uint32_t)0x00000080) |
| #define | SDADC_JCHGR_JCHG_8 ((uint32_t)0x00000100) |
| #define | SDADC_CONF0R_OFFSET0 ((uint32_t)0x00000FFF) |
| #define | SDADC_CONF0R_GAIN0 ((uint32_t)0x00700000) |
| #define | SDADC_CONF0R_GAIN0_0 ((uint32_t)0x00100000) |
| #define | SDADC_CONF0R_GAIN0_1 ((uint32_t)0x00200000) |
| #define | SDADC_CONF0R_GAIN0_2 ((uint32_t)0x00400000) |
| #define | SDADC_CONF0R_SE0 ((uint32_t)0x0C000000) |
| #define | SDADC_CONF0R_SE0_0 ((uint32_t)0x04000000) |
| #define | SDADC_CONF0R_SE0_1 ((uint32_t)0x08000000) |
| #define | SDADC_CONF0R_COMMON0 ((uint32_t)0xC0000000) |
| #define | SDADC_CONF0R_COMMON0_0 ((uint32_t)0x40000000) |
| #define | SDADC_CONF0R_COMMON0_1 ((uint32_t)0x80000000) |
| #define | SDADC_CONF1R_OFFSET1 ((uint32_t)0x00000FFF) |
| #define | SDADC_CONF1R_GAIN1 ((uint32_t)0x00700000) |
| #define | SDADC_CONF1R_GAIN1_0 ((uint32_t)0x00100000) |
| #define | SDADC_CONF1R_GAIN1_1 ((uint32_t)0x00200000) |
| #define | SDADC_CONF1R_GAIN1_2 ((uint32_t)0x00400000) |
| #define | SDADC_CONF1R_SE1 ((uint32_t)0x0C000000) |
| #define | SDADC_CONF1R_SE1_0 ((uint32_t)0x04000000) |
| #define | SDADC_CONF1R_SE1_1 ((uint32_t)0x08000000) |
| #define | SDADC_CONF1R_COMMON1 ((uint32_t)0xC0000000) |
| #define | SDADC_CONF1R_COMMON1_0 ((uint32_t)0x40000000) |
| #define | SDADC_CONF1R_COMMON1_1 ((uint32_t)0x40000000) |
| #define | SDADC_CONF2R_OFFSET2 ((uint32_t)0x00000FFF) |
| #define | SDADC_CONF2R_GAIN2 ((uint32_t)0x00700000) |
| #define | SDADC_CONF2R_GAIN2_0 ((uint32_t)0x00100000) |
| #define | SDADC_CONF2R_GAIN2_1 ((uint32_t)0x00200000) |
| #define | SDADC_CONF2R_GAIN2_2 ((uint32_t)0x00400000) |
| #define | SDADC_CONF2R_SE2 ((uint32_t)0x0C000000) |
| #define | SDADC_CONF2R_SE2_0 ((uint32_t)0x04000000) |
| #define | SDADC_CONF2R_SE2_1 ((uint32_t)0x08000000) |
| #define | SDADC_CONF2R_COMMON2 ((uint32_t)0xC0000000) |
| #define | SDADC_CONF2R_COMMON2_0 ((uint32_t)0x40000000) |
| #define | SDADC_CONF2R_COMMON2_1 ((uint32_t)0x80000000) |
| #define | SDADC_CONFCHR1_CONFCH0 ((uint32_t)0x00000003) |
| #define | SDADC_CONFCHR1_CONFCH1 ((uint32_t)0x00000030) |
| #define | SDADC_CONFCHR1_CONFCH2 ((uint32_t)0x00000300) |
| #define | SDADC_CONFCHR1_CONFCH3 ((uint32_t)0x00003000) |
| #define | SDADC_CONFCHR1_CONFCH4 ((uint32_t)0x00030000) |
| #define | SDADC_CONFCHR1_CONFCH5 ((uint32_t)0x00300000) |
| #define | SDADC_CONFCHR1_CONFCH6 ((uint32_t)0x03000000) |
| #define | SDADC_CONFCHR1_CONFCH7 ((uint32_t)0x30000000) |
| #define | SDADC_CONFCHR2_CONFCH8 ((uint32_t)0x00000003) |
| #define | SDADC_JDATAR_JDATA ((uint32_t)0x0000FFFF) |
| #define | SDADC_JDATAR_JDATACH ((uint32_t)0x0F000000) |
| #define | SDADC_JDATAR_JDATACH_0 ((uint32_t)0x01000000) |
| #define | SDADC_JDATAR_JDATACH_1 ((uint32_t)0x02000000) |
| #define | SDADC_JDATAR_JDATACH_2 ((uint32_t)0x04000000) |
| #define | SDADC_JDATAR_JDATACH_3 ((uint32_t)0x08000000) |
| #define | SDADC_RDATAR_RDATA ((uint32_t)0x0000FFFF) |
| #define | SDADC_JDATA12R_JDATA2 ((uint32_t)0xFFFF0000) |
| #define | SDADC_JDATA12R_JDATA1 ((uint32_t)0x0000FFFF) |
| #define | SDADC_RDATA12R_RDATA2 ((uint32_t)0xFFFF0000) |
| #define | SDADC_RDATA12R_RDATA1 ((uint32_t)0x0000FFFF) |
| #define | SDADC_JDATA13R_JDATA3 ((uint32_t)0xFFFF0000) |
| #define | SDADC_JDATA13R_JDATA1 ((uint32_t)0x0000FFFF) |
| #define | SDADC_RDATA13R_RDATA3 ((uint32_t)0xFFFF0000) |
| #define | SDADC_RDATA13R_RDATA1 ((uint32_t)0x0000FFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_CRCL ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint16_t)0x0001) |
| #define | SPI_CR2_TXDMAEN ((uint16_t)0x0002) |
| #define | SPI_CR2_SSOE ((uint16_t)0x0004) |
| #define | SPI_CR2_NSSP ((uint16_t)0x0008) |
| #define | SPI_CR2_FRF ((uint16_t)0x0010) |
| #define | SPI_CR2_ERRIE ((uint16_t)0x0020) |
| #define | SPI_CR2_RXNEIE ((uint16_t)0x0040) |
| #define | SPI_CR2_TXEIE ((uint16_t)0x0080) |
| #define | SPI_CR2_DS ((uint16_t)0x0F00) |
| #define | SPI_CR2_DS_0 ((uint16_t)0x0100) |
| #define | SPI_CR2_DS_1 ((uint16_t)0x0200) |
| #define | SPI_CR2_DS_2 ((uint16_t)0x0400) |
| #define | SPI_CR2_DS_3 ((uint16_t)0x0800) |
| #define | SPI_CR2_FRXTH ((uint16_t)0x1000) |
| #define | SPI_CR2_LDMARX ((uint16_t)0x2000) |
| #define | SPI_CR2_LDMATX ((uint16_t)0x4000) |
| #define | SPI_SR_RXNE ((uint16_t)0x0001) |
| #define | SPI_SR_TXE ((uint16_t)0x0002) |
| #define | SPI_SR_CHSIDE ((uint16_t)0x0004) |
| #define | SPI_SR_UDR ((uint16_t)0x0008) |
| #define | SPI_SR_CRCERR ((uint16_t)0x0010) |
| #define | SPI_SR_MODF ((uint16_t)0x0020) |
| #define | SPI_SR_OVR ((uint16_t)0x0040) |
| #define | SPI_SR_BSY ((uint16_t)0x0080) |
| #define | SPI_SR_FRE ((uint16_t)0x0100) |
| #define | SPI_SR_FRLVL ((uint16_t)0x0600) |
| #define | SPI_SR_FRLVL_0 ((uint16_t)0x0200) |
| #define | SPI_SR_FRLVL_1 ((uint16_t)0x0400) |
| #define | SPI_SR_FTLVL ((uint16_t)0x1800) |
| #define | SPI_SR_FTLVL_0 ((uint16_t)0x0800) |
| #define | SPI_SR_FTLVL_1 ((uint16_t)0x1000) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) |
| #define | SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) |
| #define | SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) |
| #define | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) |
| #define | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) |
| #define | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) |
| #define | SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) |
| #define | SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) |
| #define | SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) |
| #define | SYSCFG_CFGR1_VBAT ((uint32_t)0x01000000) |
| #define | SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) |
| #define | SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) |
| #define | SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) |
| #define | SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) |
| #define | SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) |
| #define | SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) |
| #define | SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) |
| #define | SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) |
| #define | SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) |
| #define | SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCPC ((uint16_t)0x0001) |
| #define | TIM_CR2_CCUS ((uint16_t)0x0004) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
| #define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
| #define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
| #define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
| #define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
| #define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
| #define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_OCCS ((uint16_t)0x0008) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_COMIF ((uint16_t)0x0020) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_BIF ((uint16_t)0x0080) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_COMG ((uint8_t)0x20) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_EGR_BG ((uint8_t)0x80) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
| #define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
| #define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
| #define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
| #define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
| #define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
| #define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
| #define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
| #define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
| #define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
| #define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
| #define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
| #define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
| #define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
| #define | TIM_BDTR_BKE ((uint16_t)0x1000) |
| #define | TIM_BDTR_BKP ((uint16_t)0x2000) |
| #define | TIM_BDTR_AOE ((uint16_t)0x4000) |
| #define | TIM_BDTR_MOE ((uint16_t)0x8000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM14_OR_TI1_RMP ((uint16_t)0x00C0) |
| #define | TIM14_OR_TI1_RMP_0 ((uint16_t)0x0040) |
| #define | TIM14_OR_TI1_RMP_1 ((uint16_t)0x0080) |
| #define | USART_CR1_UE ((uint32_t)0x00000001) |
| #define | USART_CR1_UESM ((uint32_t)0x00000002) |
| #define | USART_CR1_RE ((uint32_t)0x00000004) |
| #define | USART_CR1_TE ((uint32_t)0x00000008) |
| #define | USART_CR1_IDLEIE ((uint32_t)0x00000010) |
| #define | USART_CR1_RXNEIE ((uint32_t)0x00000020) |
| #define | USART_CR1_TCIE ((uint32_t)0x00000040) |
| #define | USART_CR1_TXEIE ((uint32_t)0x00000080) |
| #define | USART_CR1_PEIE ((uint32_t)0x00000100) |
| #define | USART_CR1_PS ((uint32_t)0x00000200) |
| #define | USART_CR1_PCE ((uint32_t)0x00000400) |
| #define | USART_CR1_WAKE ((uint32_t)0x00000800) |
| #define | USART_CR1_M ((uint32_t)0x00001000) |
| #define | USART_CR1_MME ((uint32_t)0x00002000) |
| #define | USART_CR1_CMIE ((uint32_t)0x00004000) |
| #define | USART_CR1_OVER8 ((uint32_t)0x00008000) |
| #define | USART_CR1_DEDT ((uint32_t)0x001F0000) |
| #define | USART_CR1_DEDT_0 ((uint32_t)0x00010000) |
| #define | USART_CR1_DEDT_1 ((uint32_t)0x00020000) |
| #define | USART_CR1_DEDT_2 ((uint32_t)0x00040000) |
| #define | USART_CR1_DEDT_3 ((uint32_t)0x00080000) |
| #define | USART_CR1_DEDT_4 ((uint32_t)0x00100000) |
| #define | USART_CR1_DEAT ((uint32_t)0x03E00000) |
| #define | USART_CR1_DEAT_0 ((uint32_t)0x00200000) |
| #define | USART_CR1_DEAT_1 ((uint32_t)0x00400000) |
| #define | USART_CR1_DEAT_2 ((uint32_t)0x00800000) |
| #define | USART_CR1_DEAT_3 ((uint32_t)0x01000000) |
| #define | USART_CR1_DEAT_4 ((uint32_t)0x02000000) |
| #define | USART_CR1_RTOIE ((uint32_t)0x04000000) |
| #define | USART_CR1_EOBIE ((uint32_t)0x08000000) |
| #define | USART_CR2_ADDM7 ((uint32_t)0x00000010) |
| #define | USART_CR2_LBDL ((uint32_t)0x00000020) |
| #define | USART_CR2_LBDIE ((uint32_t)0x00000040) |
| #define | USART_CR2_LBCL ((uint32_t)0x00000100) |
| #define | USART_CR2_CPHA ((uint32_t)0x00000200) |
| #define | USART_CR2_CPOL ((uint32_t)0x00000400) |
| #define | USART_CR2_CLKEN ((uint32_t)0x00000800) |
| #define | USART_CR2_STOP ((uint32_t)0x00003000) |
| #define | USART_CR2_STOP_0 ((uint32_t)0x00001000) |
| #define | USART_CR2_STOP_1 ((uint32_t)0x00002000) |
| #define | USART_CR2_LINEN ((uint32_t)0x00004000) |
| #define | USART_CR2_SWAP ((uint32_t)0x00008000) |
| #define | USART_CR2_RXINV ((uint32_t)0x00010000) |
| #define | USART_CR2_TXINV ((uint32_t)0x00020000) |
| #define | USART_CR2_DATAINV ((uint32_t)0x00040000) |
| #define | USART_CR2_MSBFIRST ((uint32_t)0x00080000) |
| #define | USART_CR2_ABREN ((uint32_t)0x00100000) |
| #define | USART_CR2_ABRMODE ((uint32_t)0x00600000) |
| #define | USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) |
| #define | USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) |
| #define | USART_CR2_RTOEN ((uint32_t)0x00800000) |
| #define | USART_CR2_ADD ((uint32_t)0xFF000000) |
| #define | USART_CR3_EIE ((uint32_t)0x00000001) |
| #define | USART_CR3_IREN ((uint32_t)0x00000002) |
| #define | USART_CR3_IRLP ((uint32_t)0x00000004) |
| #define | USART_CR3_HDSEL ((uint32_t)0x00000008) |
| #define | USART_CR3_NACK ((uint32_t)0x00000010) |
| #define | USART_CR3_SCEN ((uint32_t)0x00000020) |
| #define | USART_CR3_DMAR ((uint32_t)0x00000040) |
| #define | USART_CR3_DMAT ((uint32_t)0x00000080) |
| #define | USART_CR3_RTSE ((uint32_t)0x00000100) |
| #define | USART_CR3_CTSE ((uint32_t)0x00000200) |
| #define | USART_CR3_CTSIE ((uint32_t)0x00000400) |
| #define | USART_CR3_ONEBIT ((uint32_t)0x00000800) |
| #define | USART_CR3_OVRDIS ((uint32_t)0x00001000) |
| #define | USART_CR3_DDRE ((uint32_t)0x00002000) |
| #define | USART_CR3_DEM ((uint32_t)0x00004000) |
| #define | USART_CR3_DEP ((uint32_t)0x00008000) |
| #define | USART_CR3_SCARCNT ((uint32_t)0x000E0000) |
| #define | USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) |
| #define | USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) |
| #define | USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) |
| #define | USART_CR3_WUS ((uint32_t)0x00300000) |
| #define | USART_CR3_WUS_0 ((uint32_t)0x00100000) |
| #define | USART_CR3_WUS_1 ((uint32_t)0x00200000) |
| #define | USART_CR3_WUFIE ((uint32_t)0x00400000) |
| #define | USART_BRR_DIV_FRACTION ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | USART_RTOR_RTO ((uint32_t)0x00FFFFFF) |
| #define | USART_RTOR_BLEN ((uint32_t)0xFF000000) |
| #define | USART_RQR_ABRRQ ((uint16_t)0x0001) |
| #define | USART_RQR_SBKRQ ((uint16_t)0x0002) |
| #define | USART_RQR_MMRQ ((uint16_t)0x0004) |
| #define | USART_RQR_RXFRQ ((uint16_t)0x0008) |
| #define | USART_RQR_TXFRQ ((uint16_t)0x0010) |
| #define | USART_ISR_PE ((uint32_t)0x00000001) |
| #define | USART_ISR_FE ((uint32_t)0x00000002) |
| #define | USART_ISR_NE ((uint32_t)0x00000004) |
| #define | USART_ISR_ORE ((uint32_t)0x00000008) |
| #define | USART_ISR_IDLE ((uint32_t)0x00000010) |
| #define | USART_ISR_RXNE ((uint32_t)0x00000020) |
| #define | USART_ISR_TC ((uint32_t)0x00000040) |
| #define | USART_ISR_TXE ((uint32_t)0x00000080) |
| #define | USART_ISR_LBD ((uint32_t)0x00000100) |
| #define | USART_ISR_CTSIF ((uint32_t)0x00000200) |
| #define | USART_ISR_CTS ((uint32_t)0x00000400) |
| #define | USART_ISR_RTOF ((uint32_t)0x00000800) |
| #define | USART_ISR_EOBF ((uint32_t)0x00001000) |
| #define | USART_ISR_ABRE ((uint32_t)0x00004000) |
| #define | USART_ISR_ABRF ((uint32_t)0x00008000) |
| #define | USART_ISR_BUSY ((uint32_t)0x00010000) |
| #define | USART_ISR_CMF ((uint32_t)0x00020000) |
| #define | USART_ISR_SBKF ((uint32_t)0x00040000) |
| #define | USART_ISR_RWU ((uint32_t)0x00080000) |
| #define | USART_ISR_WUF ((uint32_t)0x00100000) |
| #define | USART_ISR_TEACK ((uint32_t)0x00200000) |
| #define | USART_ISR_REACK ((uint32_t)0x00400000) |
| #define | USART_ICR_PECF ((uint32_t)0x00000001) |
| #define | USART_ICR_FECF ((uint32_t)0x00000002) |
| #define | USART_ICR_NCF ((uint32_t)0x00000004) |
| #define | USART_ICR_ORECF ((uint32_t)0x00000008) |
| #define | USART_ICR_IDLECF ((uint32_t)0x00000010) |
| #define | USART_ICR_TCCF ((uint32_t)0x00000040) |
| #define | USART_ICR_LBDCF ((uint32_t)0x00000100) |
| #define | USART_ICR_CTSCF ((uint32_t)0x00000200) |
| #define | USART_ICR_RTOCF ((uint32_t)0x00000800) |
| #define | USART_ICR_EOBCF ((uint32_t)0x00001000) |
| #define | USART_ICR_CMCF ((uint32_t)0x00020000) |
| #define | USART_ICR_WUCF ((uint32_t)0x00100000) |
| #define | USART_RDR_RDR ((uint16_t)0x01FF) |
| #define | USART_TDR_TDR ((uint16_t)0x01FF) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | ADC_SR_AWD ((uint8_t)0x01) |
| #define | ADC_SR_EOC ((uint8_t)0x02) |
| #define | ADC_SR_JEOC ((uint8_t)0x04) |
| #define | ADC_SR_JSTRT ((uint8_t)0x08) |
| #define | ADC_SR_STRT ((uint8_t)0x10) |
| #define | ADC_SR_OVR ((uint8_t)0x20) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR1_RES ((uint32_t)0x03000000) |
| #define | ADC_CR1_RES_0 ((uint32_t)0x01000000) |
| #define | ADC_CR1_RES_1 ((uint32_t)0x02000000) |
| #define | ADC_CR1_OVRIE ((uint32_t)0x04000000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_DDS ((uint32_t)0x00000200) |
| #define | ADC_CR2_EOCS ((uint32_t)0x00000400) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) |
| #define | ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) |
| #define | ADC_CR2_JEXTEN ((uint32_t)0x00300000) |
| #define | ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) |
| #define | ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x0F000000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) |
| #define | ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) |
| #define | ADC_CR2_EXTEN ((uint32_t)0x30000000) |
| #define | ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) |
| #define | ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x40000000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP18 ((uint32_t)0x07000000) |
| #define | ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
| #define | ADC_HTR_HT ((uint16_t)0x0FFF) |
| #define | ADC_LTR_LT ((uint16_t)0x0FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | ADC_CSR_AWD1 ((uint32_t)0x00000001) |
| #define | ADC_CSR_EOC1 ((uint32_t)0x00000002) |
| #define | ADC_CSR_JEOC1 ((uint32_t)0x00000004) |
| #define | ADC_CSR_JSTRT1 ((uint32_t)0x00000008) |
| #define | ADC_CSR_STRT1 ((uint32_t)0x00000010) |
| #define | ADC_CSR_DOVR1 ((uint32_t)0x00000020) |
| #define | ADC_CSR_AWD2 ((uint32_t)0x00000100) |
| #define | ADC_CSR_EOC2 ((uint32_t)0x00000200) |
| #define | ADC_CSR_JEOC2 ((uint32_t)0x00000400) |
| #define | ADC_CSR_JSTRT2 ((uint32_t)0x00000800) |
| #define | ADC_CSR_STRT2 ((uint32_t)0x00001000) |
| #define | ADC_CSR_DOVR2 ((uint32_t)0x00002000) |
| #define | ADC_CSR_AWD3 ((uint32_t)0x00010000) |
| #define | ADC_CSR_EOC3 ((uint32_t)0x00020000) |
| #define | ADC_CSR_JEOC3 ((uint32_t)0x00040000) |
| #define | ADC_CSR_JSTRT3 ((uint32_t)0x00080000) |
| #define | ADC_CSR_STRT3 ((uint32_t)0x00100000) |
| #define | ADC_CSR_DOVR3 ((uint32_t)0x00200000) |
| #define | ADC_CCR_MULTI ((uint32_t)0x0000001F) |
| #define | ADC_CCR_MULTI_0 ((uint32_t)0x00000001) |
| #define | ADC_CCR_MULTI_1 ((uint32_t)0x00000002) |
| #define | ADC_CCR_MULTI_2 ((uint32_t)0x00000004) |
| #define | ADC_CCR_MULTI_3 ((uint32_t)0x00000008) |
| #define | ADC_CCR_MULTI_4 ((uint32_t)0x00000010) |
| #define | ADC_CCR_DELAY ((uint32_t)0x00000F00) |
| #define | ADC_CCR_DELAY_0 ((uint32_t)0x00000100) |
| #define | ADC_CCR_DELAY_1 ((uint32_t)0x00000200) |
| #define | ADC_CCR_DELAY_2 ((uint32_t)0x00000400) |
| #define | ADC_CCR_DELAY_3 ((uint32_t)0x00000800) |
| #define | ADC_CCR_DDS ((uint32_t)0x00002000) |
| #define | ADC_CCR_DMA ((uint32_t)0x0000C000) |
| #define | ADC_CCR_DMA_0 ((uint32_t)0x00004000) |
| #define | ADC_CCR_DMA_1 ((uint32_t)0x00008000) |
| #define | ADC_CCR_ADCPRE ((uint32_t)0x00030000) |
| #define | ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) |
| #define | ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) |
| #define | ADC_CCR_VBATE ((uint32_t)0x00400000) |
| #define | ADC_CCR_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) |
| #define | ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) |
| #define | CAN_MCR_INRQ ((uint16_t)0x0001) |
| #define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
| #define | CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define | CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define | CAN_MCR_NART ((uint16_t)0x0010) |
| #define | CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define | CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define | CAN_MCR_TTCM ((uint16_t)0x0080) |
| #define | CAN_MCR_RESET ((uint16_t)0x8000) |
| #define | CAN_MSR_INAK ((uint16_t)0x0001) |
| #define | CAN_MSR_SLAK ((uint16_t)0x0002) |
| #define | CAN_MSR_ERRI ((uint16_t)0x0004) |
| #define | CAN_MSR_WKUI ((uint16_t)0x0008) |
| #define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
| #define | CAN_MSR_TXM ((uint16_t)0x0100) |
| #define | CAN_MSR_RXM ((uint16_t)0x0200) |
| #define | CAN_MSR_SAMP ((uint16_t)0x0400) |
| #define | CAN_MSR_RX ((uint16_t)0x0800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
| #define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
| #define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
| #define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
| #define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
| #define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
| #define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
| #define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint8_t)0x01) |
| #define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
| #define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
| #define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
| #define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
| #define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
| #define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
| #define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
| #define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
| #define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
| #define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
| #define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
| #define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
| #define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
| #define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
| #define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
| #define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
| #define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
| #define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
| #define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
| #define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
| #define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
| #define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
| #define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
| #define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
| #define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
| #define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
| #define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
| #define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
| #define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
| #define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
| #define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
| #define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
| #define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
| #define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
| #define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
| #define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
| #define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
| #define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
| #define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
| #define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
| #define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
| #define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
| #define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
| #define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
| #define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
| #define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
| #define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
| #define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
| #define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
| #define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
| #define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
| #define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
| #define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
| #define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
| #define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
| #define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
| #define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
| #define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
| #define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
| #define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint8_t)0x01) |
| #define | CRYP_CR_ALGODIR ((uint32_t)0x00000004) |
| #define | CRYP_CR_ALGOMODE ((uint32_t)0x00000038) |
| #define | CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) |
| #define | CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) |
| #define | CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) |
| #define | CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) |
| #define | CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) |
| #define | CRYP_CR_DATATYPE ((uint32_t)0x000000C0) |
| #define | CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) |
| #define | CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) |
| #define | CRYP_CR_KEYSIZE ((uint32_t)0x00000300) |
| #define | CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) |
| #define | CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) |
| #define | CRYP_CR_FFLUSH ((uint32_t)0x00004000) |
| #define | CRYP_CR_CRYPEN ((uint32_t)0x00008000) |
| #define | CRYP_SR_IFEM ((uint32_t)0x00000001) |
| #define | CRYP_SR_IFNF ((uint32_t)0x00000002) |
| #define | CRYP_SR_OFNE ((uint32_t)0x00000004) |
| #define | CRYP_SR_OFFU ((uint32_t)0x00000008) |
| #define | CRYP_SR_BUSY ((uint32_t)0x00000010) |
| #define | CRYP_DMACR_DIEN ((uint32_t)0x00000001) |
| #define | CRYP_DMACR_DOEN ((uint32_t)0x00000002) |
| #define | CRYP_IMSCR_INIM ((uint32_t)0x00000001) |
| #define | CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) |
| #define | CRYP_RISR_OUTRIS ((uint32_t)0x00000001) |
| #define | CRYP_RISR_INRIS ((uint32_t)0x00000002) |
| #define | CRYP_MISR_INMIS ((uint32_t)0x00000001) |
| #define | CRYP_MISR_OUTMIS ((uint32_t)0x00000002) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | DCMI_CR_CAPTURE ((uint32_t)0x00000001) |
| #define | DCMI_CR_CM ((uint32_t)0x00000002) |
| #define | DCMI_CR_CROP ((uint32_t)0x00000004) |
| #define | DCMI_CR_JPEG ((uint32_t)0x00000008) |
| #define | DCMI_CR_ESS ((uint32_t)0x00000010) |
| #define | DCMI_CR_PCKPOL ((uint32_t)0x00000020) |
| #define | DCMI_CR_HSPOL ((uint32_t)0x00000040) |
| #define | DCMI_CR_VSPOL ((uint32_t)0x00000080) |
| #define | DCMI_CR_FCRC_0 ((uint32_t)0x00000100) |
| #define | DCMI_CR_FCRC_1 ((uint32_t)0x00000200) |
| #define | DCMI_CR_EDM_0 ((uint32_t)0x00000400) |
| #define | DCMI_CR_EDM_1 ((uint32_t)0x00000800) |
| #define | DCMI_CR_CRE ((uint32_t)0x00001000) |
| #define | DCMI_CR_ENABLE ((uint32_t)0x00004000) |
| #define | DCMI_SR_HSYNC ((uint32_t)0x00000001) |
| #define | DCMI_SR_VSYNC ((uint32_t)0x00000002) |
| #define | DCMI_SR_FNE ((uint32_t)0x00000004) |
| #define | DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) |
| #define | DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) |
| #define | DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) |
| #define | DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) |
| #define | DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) |
| #define | DCMI_IER_FRAME_IE ((uint32_t)0x00000001) |
| #define | DCMI_IER_OVF_IE ((uint32_t)0x00000002) |
| #define | DCMI_IER_ERR_IE ((uint32_t)0x00000004) |
| #define | DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) |
| #define | DCMI_IER_LINE_IE ((uint32_t)0x00000010) |
| #define | DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) |
| #define | DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) |
| #define | DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) |
| #define | DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) |
| #define | DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) |
| #define | DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) |
| #define | DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) |
| #define | DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) |
| #define | DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) |
| #define | DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) |
| #define | DMA_SxCR_CHSEL ((uint32_t)0x0E000000) |
| #define | DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) |
| #define | DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) |
| #define | DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) |
| #define | DMA_SxCR_MBURST ((uint32_t)0x01800000) |
| #define | DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) |
| #define | DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) |
| #define | DMA_SxCR_PBURST ((uint32_t)0x00600000) |
| #define | DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) |
| #define | DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) |
| #define | DMA_SxCR_ACK ((uint32_t)0x00100000) |
| #define | DMA_SxCR_CT ((uint32_t)0x00080000) |
| #define | DMA_SxCR_DBM ((uint32_t)0x00040000) |
| #define | DMA_SxCR_PL ((uint32_t)0x00030000) |
| #define | DMA_SxCR_PL_0 ((uint32_t)0x00010000) |
| #define | DMA_SxCR_PL_1 ((uint32_t)0x00020000) |
| #define | DMA_SxCR_PINCOS ((uint32_t)0x00008000) |
| #define | DMA_SxCR_MSIZE ((uint32_t)0x00006000) |
| #define | DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) |
| #define | DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) |
| #define | DMA_SxCR_PSIZE ((uint32_t)0x00001800) |
| #define | DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) |
| #define | DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) |
| #define | DMA_SxCR_MINC ((uint32_t)0x00000400) |
| #define | DMA_SxCR_PINC ((uint32_t)0x00000200) |
| #define | DMA_SxCR_CIRC ((uint32_t)0x00000100) |
| #define | DMA_SxCR_DIR ((uint32_t)0x000000C0) |
| #define | DMA_SxCR_DIR_0 ((uint32_t)0x00000040) |
| #define | DMA_SxCR_DIR_1 ((uint32_t)0x00000080) |
| #define | DMA_SxCR_PFCTRL ((uint32_t)0x00000020) |
| #define | DMA_SxCR_TCIE ((uint32_t)0x00000010) |
| #define | DMA_SxCR_HTIE ((uint32_t)0x00000008) |
| #define | DMA_SxCR_TEIE ((uint32_t)0x00000004) |
| #define | DMA_SxCR_DMEIE ((uint32_t)0x00000002) |
| #define | DMA_SxCR_EN ((uint32_t)0x00000001) |
| #define | DMA_SxNDT ((uint32_t)0x0000FFFF) |
| #define | DMA_SxNDT_0 ((uint32_t)0x00000001) |
| #define | DMA_SxNDT_1 ((uint32_t)0x00000002) |
| #define | DMA_SxNDT_2 ((uint32_t)0x00000004) |
| #define | DMA_SxNDT_3 ((uint32_t)0x00000008) |
| #define | DMA_SxNDT_4 ((uint32_t)0x00000010) |
| #define | DMA_SxNDT_5 ((uint32_t)0x00000020) |
| #define | DMA_SxNDT_6 ((uint32_t)0x00000040) |
| #define | DMA_SxNDT_7 ((uint32_t)0x00000080) |
| #define | DMA_SxNDT_8 ((uint32_t)0x00000100) |
| #define | DMA_SxNDT_9 ((uint32_t)0x00000200) |
| #define | DMA_SxNDT_10 ((uint32_t)0x00000400) |
| #define | DMA_SxNDT_11 ((uint32_t)0x00000800) |
| #define | DMA_SxNDT_12 ((uint32_t)0x00001000) |
| #define | DMA_SxNDT_13 ((uint32_t)0x00002000) |
| #define | DMA_SxNDT_14 ((uint32_t)0x00004000) |
| #define | DMA_SxNDT_15 ((uint32_t)0x00008000) |
| #define | DMA_SxFCR_FEIE ((uint32_t)0x00000080) |
| #define | DMA_SxFCR_FS ((uint32_t)0x00000038) |
| #define | DMA_SxFCR_FS_0 ((uint32_t)0x00000008) |
| #define | DMA_SxFCR_FS_1 ((uint32_t)0x00000010) |
| #define | DMA_SxFCR_FS_2 ((uint32_t)0x00000020) |
| #define | DMA_SxFCR_DMDIS ((uint32_t)0x00000004) |
| #define | DMA_SxFCR_FTH ((uint32_t)0x00000003) |
| #define | DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) |
| #define | DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) |
| #define | DMA_LISR_TCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LISR_HTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LISR_TEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LISR_DMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LISR_FEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LISR_TCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LISR_HTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LISR_TEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LISR_DMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LISR_FEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LISR_TCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LISR_HTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LISR_TEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LISR_DMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LISR_FEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LISR_TCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LISR_HTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LISR_TEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LISR_DMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LISR_FEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HISR_TCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HISR_TEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HISR_DMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HISR_FEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HISR_HTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HISR_TEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HISR_DMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HISR_FEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HISR_TCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HISR_HTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HISR_TEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HISR_DMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HISR_FEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HISR_TCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HISR_HTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HISR_TEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HISR_DMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HISR_FEIF4 ((uint32_t)0x00000001) |
| #define | DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
| #define | FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
| #define | FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
| #define | FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) |
| #define | FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) |
| #define | FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) |
| #define | FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
| #define | FLASH_ACR_ICEN ((uint32_t)0x00000200) |
| #define | FLASH_ACR_DCEN ((uint32_t)0x00000400) |
| #define | FLASH_ACR_ICRST ((uint32_t)0x00000800) |
| #define | FLASH_ACR_DCRST ((uint32_t)0x00001000) |
| #define | FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) |
| #define | FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000001) |
| #define | FLASH_SR_SOP ((uint32_t)0x00000002) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_PGAERR ((uint32_t)0x00000020) |
| #define | FLASH_SR_PGPERR ((uint32_t)0x00000040) |
| #define | FLASH_SR_PGSERR ((uint32_t)0x00000080) |
| #define | FLASH_SR_BSY ((uint32_t)0x00010000) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_SER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_SNB_0 ((uint32_t)0x00000008) |
| #define | FLASH_CR_SNB_1 ((uint32_t)0x00000010) |
| #define | FLASH_CR_SNB_2 ((uint32_t)0x00000020) |
| #define | FLASH_CR_SNB_3 ((uint32_t)0x00000040) |
| #define | FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | FLASH_CR_STRT ((uint32_t)0x00010000) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x01000000) |
| #define | FLASH_CR_LOCK ((uint32_t)0x80000000) |
| #define | FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) |
| #define | FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) |
| #define | FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) |
| #define | FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) |
| #define | FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) |
| #define | FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) |
| #define | FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) |
| #define | FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) |
| #define | FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) |
| #define | FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) |
| #define | FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) |
| #define | FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) |
| #define | FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) |
| #define | FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) |
| #define | FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) |
| #define | FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) |
| #define | FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) |
| #define | FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) |
| #define | FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) |
| #define | FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) |
| #define | FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) |
| #define | FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) |
| #define | FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) |
| #define | FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) |
| #define | FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) |
| #define | FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) |
| #define | FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) |
| #define | FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) |
| #define | FSMC_BCR1_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR1_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR1_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR1_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR1_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR1_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR1_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR2_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR2_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR2_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR2_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR2_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR2_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR2_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR3_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR3_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR3_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR3_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR3_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR3_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR3_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR4_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR4_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR4_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR4_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR4_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR4_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR4_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR2_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR2_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR2_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR2_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR2_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR2_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR3_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR3_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR3_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR3_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR3_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR3_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) |
| #define | FSMC_PCR4_PBKEN ((uint32_t)0x00000004) |
| #define | FSMC_PCR4_PTYP ((uint32_t)0x00000008) |
| #define | FSMC_PCR4_PWID ((uint32_t)0x00000030) |
| #define | FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_PCR4_ECCEN ((uint32_t)0x00000040) |
| #define | FSMC_PCR4_TCLR ((uint32_t)0x00001E00) |
| #define | FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) |
| #define | FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) |
| #define | FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) |
| #define | FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) |
| #define | FSMC_PCR4_TAR ((uint32_t)0x0001E000) |
| #define | FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) |
| #define | FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) |
| #define | FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) |
| #define | FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) |
| #define | FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) |
| #define | FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) |
| #define | FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) |
| #define | FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) |
| #define | FSMC_SR2_IRS ((uint8_t)0x01) |
| #define | FSMC_SR2_ILS ((uint8_t)0x02) |
| #define | FSMC_SR2_IFS ((uint8_t)0x04) |
| #define | FSMC_SR2_IREN ((uint8_t)0x08) |
| #define | FSMC_SR2_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR2_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR2_FEMPT ((uint8_t)0x40) |
| #define | FSMC_SR3_IRS ((uint8_t)0x01) |
| #define | FSMC_SR3_ILS ((uint8_t)0x02) |
| #define | FSMC_SR3_IFS ((uint8_t)0x04) |
| #define | FSMC_SR3_IREN ((uint8_t)0x08) |
| #define | FSMC_SR3_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR3_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR3_FEMPT ((uint8_t)0x40) |
| #define | FSMC_SR4_IRS ((uint8_t)0x01) |
| #define | FSMC_SR4_ILS ((uint8_t)0x02) |
| #define | FSMC_SR4_IFS ((uint8_t)0x04) |
| #define | FSMC_SR4_IREN ((uint8_t)0x08) |
| #define | FSMC_SR4_ILEN ((uint8_t)0x10) |
| #define | FSMC_SR4_IFEN ((uint8_t)0x20) |
| #define | FSMC_SR4_FEMPT ((uint8_t)0x40) |
| #define | FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) |
| #define | FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) |
| #define | FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) |
| #define | FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) |
| #define | FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) |
| #define | FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) |
| #define | FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) |
| #define | FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) |
| #define | FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) |
| #define | FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) |
| #define | FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) |
| #define | FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) |
| #define | FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) |
| #define | FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) |
| #define | FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) |
| #define | FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) |
| #define | FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) |
| #define | FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) |
| #define | FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) |
| #define | FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) |
| #define | FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) |
| #define | FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) |
| #define | FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) |
| #define | FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) |
| #define | FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) |
| #define | FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) |
| #define | FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) |
| #define | FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) |
| #define | FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) |
| #define | FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) |
| #define | FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) |
| #define | FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) |
| #define | FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) |
| #define | FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) |
| #define | FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) |
| #define | FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) |
| #define | FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) |
| #define | FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) |
| #define | FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) |
| #define | FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | HASH_CR_INIT ((uint32_t)0x00000004) |
| #define | HASH_CR_DMAE ((uint32_t)0x00000008) |
| #define | HASH_CR_DATATYPE ((uint32_t)0x00000030) |
| #define | HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) |
| #define | HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) |
| #define | HASH_CR_MODE ((uint32_t)0x00000040) |
| #define | HASH_CR_ALGO ((uint32_t)0x00000080) |
| #define | HASH_CR_NBW ((uint32_t)0x00000F00) |
| #define | HASH_CR_NBW_0 ((uint32_t)0x00000100) |
| #define | HASH_CR_NBW_1 ((uint32_t)0x00000200) |
| #define | HASH_CR_NBW_2 ((uint32_t)0x00000400) |
| #define | HASH_CR_NBW_3 ((uint32_t)0x00000800) |
| #define | HASH_CR_DINNE ((uint32_t)0x00001000) |
| #define | HASH_CR_LKEY ((uint32_t)0x00010000) |
| #define | HASH_STR_NBW ((uint32_t)0x0000001F) |
| #define | HASH_STR_NBW_0 ((uint32_t)0x00000001) |
| #define | HASH_STR_NBW_1 ((uint32_t)0x00000002) |
| #define | HASH_STR_NBW_2 ((uint32_t)0x00000004) |
| #define | HASH_STR_NBW_3 ((uint32_t)0x00000008) |
| #define | HASH_STR_NBW_4 ((uint32_t)0x00000010) |
| #define | HASH_STR_DCAL ((uint32_t)0x00000100) |
| #define | HASH_IMR_DINIM ((uint32_t)0x00000001) |
| #define | HASH_IMR_DCIM ((uint32_t)0x00000002) |
| #define | HASH_SR_DINIS ((uint32_t)0x00000001) |
| #define | HASH_SR_DCIS ((uint32_t)0x00000002) |
| #define | HASH_SR_DMAS ((uint32_t)0x00000004) |
| #define | HASH_SR_BUSY ((uint32_t)0x00000008) |
| #define | I2C_CR1_PE ((uint16_t)0x0001) |
| #define | I2C_CR1_SMBUS ((uint16_t)0x0002) |
| #define | I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
| #define | I2C_CR1_ENARP ((uint16_t)0x0010) |
| #define | I2C_CR1_ENPEC ((uint16_t)0x0020) |
| #define | I2C_CR1_ENGC ((uint16_t)0x0040) |
| #define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
| #define | I2C_CR1_START ((uint16_t)0x0100) |
| #define | I2C_CR1_STOP ((uint16_t)0x0200) |
| #define | I2C_CR1_ACK ((uint16_t)0x0400) |
| #define | I2C_CR1_POS ((uint16_t)0x0800) |
| #define | I2C_CR1_PEC ((uint16_t)0x1000) |
| #define | I2C_CR1_ALERT ((uint16_t)0x2000) |
| #define | I2C_CR1_SWRST ((uint16_t)0x8000) |
| #define | I2C_CR2_FREQ ((uint16_t)0x003F) |
| #define | I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
| #define | I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
| #define | I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
| #define | I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
| #define | I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
| #define | I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
| #define | I2C_CR2_ITERREN ((uint16_t)0x0100) |
| #define | I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
| #define | I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
| #define | I2C_CR2_DMAEN ((uint16_t)0x0800) |
| #define | I2C_CR2_LAST ((uint16_t)0x1000) |
| #define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
| #define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
| #define | I2C_OAR1_ADD0 ((uint16_t)0x0001) |
| #define | I2C_OAR1_ADD1 ((uint16_t)0x0002) |
| #define | I2C_OAR1_ADD2 ((uint16_t)0x0004) |
| #define | I2C_OAR1_ADD3 ((uint16_t)0x0008) |
| #define | I2C_OAR1_ADD4 ((uint16_t)0x0010) |
| #define | I2C_OAR1_ADD5 ((uint16_t)0x0020) |
| #define | I2C_OAR1_ADD6 ((uint16_t)0x0040) |
| #define | I2C_OAR1_ADD7 ((uint16_t)0x0080) |
| #define | I2C_OAR1_ADD8 ((uint16_t)0x0100) |
| #define | I2C_OAR1_ADD9 ((uint16_t)0x0200) |
| #define | I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
| #define | I2C_OAR2_ENDUAL ((uint8_t)0x01) |
| #define | I2C_OAR2_ADD2 ((uint8_t)0xFE) |
| #define | I2C_DR_DR ((uint8_t)0xFF) |
| #define | I2C_SR1_SB ((uint16_t)0x0001) |
| #define | I2C_SR1_ADDR ((uint16_t)0x0002) |
| #define | I2C_SR1_BTF ((uint16_t)0x0004) |
| #define | I2C_SR1_ADD10 ((uint16_t)0x0008) |
| #define | I2C_SR1_STOPF ((uint16_t)0x0010) |
| #define | I2C_SR1_RXNE ((uint16_t)0x0040) |
| #define | I2C_SR1_TXE ((uint16_t)0x0080) |
| #define | I2C_SR1_BERR ((uint16_t)0x0100) |
| #define | I2C_SR1_ARLO ((uint16_t)0x0200) |
| #define | I2C_SR1_AF ((uint16_t)0x0400) |
| #define | I2C_SR1_OVR ((uint16_t)0x0800) |
| #define | I2C_SR1_PECERR ((uint16_t)0x1000) |
| #define | I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
| #define | I2C_SR1_SMBALERT ((uint16_t)0x8000) |
| #define | I2C_SR2_MSL ((uint16_t)0x0001) |
| #define | I2C_SR2_BUSY ((uint16_t)0x0002) |
| #define | I2C_SR2_TRA ((uint16_t)0x0004) |
| #define | I2C_SR2_GENCALL ((uint16_t)0x0010) |
| #define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
| #define | I2C_SR2_SMBHOST ((uint16_t)0x0040) |
| #define | I2C_SR2_DUALF ((uint16_t)0x0080) |
| #define | I2C_SR2_PEC ((uint16_t)0xFF00) |
| #define | I2C_CCR_CCR ((uint16_t)0x0FFF) |
| #define | I2C_CCR_DUTY ((uint16_t)0x4000) |
| #define | I2C_CCR_FS ((uint16_t)0x8000) |
| #define | I2C_TRISE_TRISE ((uint8_t)0x3F) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | PWR_CR_LPDS ((uint16_t)0x0001) |
| #define | PWR_CR_PDDS ((uint16_t)0x0002) |
| #define | PWR_CR_CWUF ((uint16_t)0x0004) |
| #define | PWR_CR_CSBF ((uint16_t)0x0008) |
| #define | PWR_CR_PVDE ((uint16_t)0x0010) |
| #define | PWR_CR_PLS ((uint16_t)0x00E0) |
| #define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV0 ((uint16_t)0x0000) |
| #define | PWR_CR_PLS_LEV1 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_LEV2 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_LEV3 ((uint16_t)0x0060) |
| #define | PWR_CR_PLS_LEV4 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) |
| #define | PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) |
| #define | PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) |
| #define | PWR_CR_DBP ((uint16_t)0x0100) |
| #define | PWR_CR_FPDS ((uint16_t)0x0200) |
| #define | PWR_CSR_WUF ((uint16_t)0x0001) |
| #define | PWR_CSR_SBF ((uint16_t)0x0002) |
| #define | PWR_CSR_PVDO ((uint16_t)0x0004) |
| #define | PWR_CSR_BRR ((uint16_t)0x0008) |
| #define | PWR_CSR_EWUP ((uint16_t)0x0100) |
| #define | PWR_CSR_BRE ((uint16_t)0x0200) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) |
| #define | RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) |
| #define | RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) |
| #define | RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) |
| #define | RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSICAL_0 ((uint32_t)0x00000100) |
| #define | RCC_CR_HSICAL_1 ((uint32_t)0x00000200) |
| #define | RCC_CR_HSICAL_2 ((uint32_t)0x00000400) |
| #define | RCC_CR_HSICAL_3 ((uint32_t)0x00000800) |
| #define | RCC_CR_HSICAL_4 ((uint32_t)0x00001000) |
| #define | RCC_CR_HSICAL_5 ((uint32_t)0x00002000) |
| #define | RCC_CR_HSICAL_6 ((uint32_t)0x00004000) |
| #define | RCC_CR_HSICAL_7 ((uint32_t)0x00008000) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CR_PLLI2SON ((uint32_t)0x04000000) |
| #define | RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) |
| #define | RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) |
| #define | RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) |
| #define | RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) |
| #define | RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) |
| #define | RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) |
| #define | RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) |
| #define | RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) |
| #define | RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) |
| #define | RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) |
| #define | RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) |
| #define | RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) |
| #define | RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) |
| #define | RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) |
| #define | RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) |
| #define | RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) |
| #define | RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) |
| #define | RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) |
| #define | RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) |
| #define | RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) |
| #define | RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
| #define | RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) |
| #define | RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) |
| #define | RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) |
| #define | RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E00) |
| #define | RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) |
| #define | RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) |
| #define | RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_MCO1 ((uint32_t)0x00600000) |
| #define | RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) |
| #define | RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
| #define | RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) |
| #define | RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_MCO2 ((uint32_t)0xC0000000) |
| #define | RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) |
| #define | RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) |
| #define | RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) |
| #define | RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) |
| #define | RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) |
| #define | RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) |
| #define | RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) |
| #define | RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) |
| #define | RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) |
| #define | RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
| #define | RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) |
| #define | RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) |
| #define | RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) |
| #define | RCC_AHB1RSTR_OTGHSRST ((uint32_t)0x10000000) |
| #define | RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) |
| #define | RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) |
| #define | RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020) |
| #define | RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) |
| #define | RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) |
| #define | RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1 ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) |
| #define | RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) |
| #define | RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) |
| #define | RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) |
| #define | RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) |
| #define | RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) |
| #define | RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) |
| #define | RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) |
| #define | RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) |
| #define | RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) |
| #define | RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) |
| #define | RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) |
| #define | RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
| #define | RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
| #define | RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) |
| #define | RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) |
| #define | RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
| #define | RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
| #define | RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
| #define | RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
| #define | RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
| #define | RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
| #define | RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
| #define | RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) |
| #define | RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) |
| #define | RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) |
| #define | RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
| #define | RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
| #define | RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) |
| #define | RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) |
| #define | RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
| #define | RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) |
| #define | RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) |
| #define | RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_BORRSTF ((uint32_t)0x02000000) |
| #define | RCC_CSR_PADRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_WDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) |
| #define | RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) |
| #define | RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) |
| #define | RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) |
| #define | RNG_CR_RNGEN ((uint32_t)0x00000004) |
| #define | RNG_CR_IE ((uint32_t)0x00000008) |
| #define | RNG_SR_DRDY ((uint32_t)0x00000001) |
| #define | RNG_SR_CECS ((uint32_t)0x00000002) |
| #define | RNG_SR_SECS ((uint32_t)0x00000004) |
| #define | RNG_SR_CEIS ((uint32_t)0x00000020) |
| #define | RNG_SR_SEIS ((uint32_t)0x00000040) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_WUTIE ((uint32_t)0x00004000) |
| #define | RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_WUTE ((uint32_t)0x00000400) |
| #define | RTC_CR_ALRBE ((uint32_t)0x00000200) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_DCE ((uint32_t)0x00000080) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| #define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| #define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| #define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_WUTF ((uint32_t)0x00000400) |
| #define | RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| #define | RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) |
| #define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| #define | RTC_CALIBR_DCS ((uint32_t)0x00000080) |
| #define | RTC_CALIBR_DC ((uint32_t)0x0000001F) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) |
| #define | RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint16_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint16_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_DFF ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint8_t)0x01) |
| #define | SPI_CR2_TXDMAEN ((uint8_t)0x02) |
| #define | SPI_CR2_SSOE ((uint8_t)0x04) |
| #define | SPI_CR2_ERRIE ((uint8_t)0x20) |
| #define | SPI_CR2_RXNEIE ((uint8_t)0x40) |
| #define | SPI_CR2_TXEIE ((uint8_t)0x80) |
| #define | SPI_SR_RXNE ((uint8_t)0x01) |
| #define | SPI_SR_TXE ((uint8_t)0x02) |
| #define | SPI_SR_CHSIDE ((uint8_t)0x04) |
| #define | SPI_SR_UDR ((uint8_t)0x08) |
| #define | SPI_SR_CRCERR ((uint8_t)0x10) |
| #define | SPI_SR_MODF ((uint8_t)0x20) |
| #define | SPI_SR_OVR ((uint8_t)0x40) |
| #define | SPI_SR_BSY ((uint8_t)0x80) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) |
| #define | SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) |
| #define | SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) |
| #define | SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) |
| #define | SYSCFG_CMPCR_READY ((uint32_t)0x00000100) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCPC ((uint16_t)0x0001) |
| #define | TIM_CR2_CCUS ((uint16_t)0x0004) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
| #define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
| #define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
| #define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
| #define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
| #define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
| #define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_COMIF ((uint16_t)0x0020) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_BIF ((uint16_t)0x0080) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_COMG ((uint8_t)0x20) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_EGR_BG ((uint8_t)0x80) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
| #define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
| #define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
| #define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
| #define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
| #define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
| #define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
| #define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
| #define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
| #define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
| #define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
| #define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
| #define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
| #define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
| #define | TIM_BDTR_BKE ((uint16_t)0x1000) |
| #define | TIM_BDTR_BKP ((uint16_t)0x2000) |
| #define | TIM_BDTR_AOE ((uint16_t)0x4000) |
| #define | TIM_BDTR_MOE ((uint16_t)0x8000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM_OR_TI4_RMP ((uint16_t)0x00C0) |
| #define | TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) |
| #define | TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) |
| #define | TIM_OR_ITR1_RMP ((uint16_t)0x0C00) |
| #define | TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) |
| #define | TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) |
| #define | USART_SR_PE ((uint16_t)0x0001) |
| #define | USART_SR_FE ((uint16_t)0x0002) |
| #define | USART_SR_NE ((uint16_t)0x0004) |
| #define | USART_SR_ORE ((uint16_t)0x0008) |
| #define | USART_SR_IDLE ((uint16_t)0x0010) |
| #define | USART_SR_RXNE ((uint16_t)0x0020) |
| #define | USART_SR_TC ((uint16_t)0x0040) |
| #define | USART_SR_TXE ((uint16_t)0x0080) |
| #define | USART_SR_LBD ((uint16_t)0x0100) |
| #define | USART_SR_CTS ((uint16_t)0x0200) |
| #define | USART_DR_DR ((uint16_t)0x01FF) |
| #define | USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
| #define | USART_CR1_SBK ((uint16_t)0x0001) |
| #define | USART_CR1_RWU ((uint16_t)0x0002) |
| #define | USART_CR1_RE ((uint16_t)0x0004) |
| #define | USART_CR1_TE ((uint16_t)0x0008) |
| #define | USART_CR1_IDLEIE ((uint16_t)0x0010) |
| #define | USART_CR1_RXNEIE ((uint16_t)0x0020) |
| #define | USART_CR1_TCIE ((uint16_t)0x0040) |
| #define | USART_CR1_TXEIE ((uint16_t)0x0080) |
| #define | USART_CR1_PEIE ((uint16_t)0x0100) |
| #define | USART_CR1_PS ((uint16_t)0x0200) |
| #define | USART_CR1_PCE ((uint16_t)0x0400) |
| #define | USART_CR1_WAKE ((uint16_t)0x0800) |
| #define | USART_CR1_M ((uint16_t)0x1000) |
| #define | USART_CR1_UE ((uint16_t)0x2000) |
| #define | USART_CR1_OVER8 ((uint16_t)0x8000) |
| #define | USART_CR2_ADD ((uint16_t)0x000F) |
| #define | USART_CR2_LBDL ((uint16_t)0x0020) |
| #define | USART_CR2_LBDIE ((uint16_t)0x0040) |
| #define | USART_CR2_LBCL ((uint16_t)0x0100) |
| #define | USART_CR2_CPHA ((uint16_t)0x0200) |
| #define | USART_CR2_CPOL ((uint16_t)0x0400) |
| #define | USART_CR2_CLKEN ((uint16_t)0x0800) |
| #define | USART_CR2_STOP ((uint16_t)0x3000) |
| #define | USART_CR2_STOP_0 ((uint16_t)0x1000) |
| #define | USART_CR2_STOP_1 ((uint16_t)0x2000) |
| #define | USART_CR2_LINEN ((uint16_t)0x4000) |
| #define | USART_CR3_EIE ((uint16_t)0x0001) |
| #define | USART_CR3_IREN ((uint16_t)0x0002) |
| #define | USART_CR3_IRLP ((uint16_t)0x0004) |
| #define | USART_CR3_HDSEL ((uint16_t)0x0008) |
| #define | USART_CR3_NACK ((uint16_t)0x0010) |
| #define | USART_CR3_SCEN ((uint16_t)0x0020) |
| #define | USART_CR3_DMAR ((uint16_t)0x0040) |
| #define | USART_CR3_DMAT ((uint16_t)0x0080) |
| #define | USART_CR3_RTSE ((uint16_t)0x0100) |
| #define | USART_CR3_CTSE ((uint16_t)0x0200) |
| #define | USART_CR3_CTSIE ((uint16_t)0x0400) |
| #define | USART_CR3_ONEBIT ((uint16_t)0x0800) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_PSC_0 ((uint16_t)0x0001) |
| #define | USART_GTPR_PSC_1 ((uint16_t)0x0002) |
| #define | USART_GTPR_PSC_2 ((uint16_t)0x0004) |
| #define | USART_GTPR_PSC_3 ((uint16_t)0x0008) |
| #define | USART_GTPR_PSC_4 ((uint16_t)0x0010) |
| #define | USART_GTPR_PSC_5 ((uint16_t)0x0020) |
| #define | USART_GTPR_PSC_6 ((uint16_t)0x0040) |
| #define | USART_GTPR_PSC_7 ((uint16_t)0x0080) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| #define | DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
| #define | DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDEG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) |
| #define | DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) |
| #define | ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
| #define | ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
| #define | ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
| #define | ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
| #define | ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
| #define | ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
| #define | ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
| #define | ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
| #define | ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
| #define | ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
| #define | ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
| #define | ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
| #define | ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
| #define | ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
| #define | ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
| #define | ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
| #define | ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
| #define | ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
| #define | ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
| #define | ETH_MACCR_BL |
| #define | ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
| #define | ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
| #define | ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
| #define | ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
| #define | ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
| #define | ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
| #define | ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
| #define | ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
| #define | ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
| #define | ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
| #define | ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
| #define | ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
| #define | ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
| #define | ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| #define | ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
| #define | ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
| #define | ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
| #define | ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
| #define | ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
| #define | ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
| #define | ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
| #define | ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
| #define | ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
| #define | ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
| #define | ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
| #define | ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
| #define | ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
| #define | ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-120 MHz; MDC clock= HCLK/62 */ |
| #define | ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| #define | ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/42 */ |
| #define | ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
| #define | ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
| #define | ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
| #define | ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
| #define | ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
| #define | ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
| #define | ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
| #define | ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
| #define | ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
| #define | ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
| #define | ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
| #define | ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
| #define | ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
| #define | ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
| #define | ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
| #define | ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
| #define | ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
| #define | ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
| #define | ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
| #define | ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
| #define | ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
| #define | ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
| #define | ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
| #define | ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
| #define | ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
| #define | ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
| #define | ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
| #define | ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
| #define | ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
| #define | ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
| #define | ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
| #define | ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
| #define | ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
| #define | ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| #define | ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
| #define | ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
| #define | ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
| #define | ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
| #define | ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
| #define | ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset (Only in STM32F2xx) */ |
| #define | ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset (Only in STM32F2xx) */ |
| #define | ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
| #define | ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
| #define | ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
| #define | ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
| #define | ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
| #define | ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
| #define | ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
| #define | ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
| #define | ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ |
| #define | ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ |
| #define | ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ |
| #define | ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ |
| #define | ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ |
| #define | ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ |
| #define | ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ |
| #define | ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ |
| #define | ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ |
| #define | ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
| #define | ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
| #define | ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
| #define | ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
| #define | ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
| #define | ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
| #define | ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
| #define | ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
| #define | ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
| #define | ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
| #define | ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
| #define | ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
| #define | ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
| #define | ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
| #define | ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
| #define | ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
| #define | ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ |
| #define | ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ |
| #define | ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
| #define | ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
| #define | ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
| #define | ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
| #define | ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| #define | ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| #define | ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| #define | ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| #define | ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
| #define | ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
| #define | ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| #define | ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| #define | ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| #define | ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| #define | ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ |
| #define | ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
| #define | ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
| #define | ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
| #define | ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
| #define | ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
| #define | ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
| #define | ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
| #define | ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
| #define | ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
| #define | ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
| #define | ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
| #define | ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
| #define | ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
| #define | ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| #define | ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
| #define | ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
| #define | ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
| #define | ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
| #define | ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
| #define | ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
| #define | ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
| #define | ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
| #define | ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
| #define | ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
| #define | ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
| #define | ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
| #define | ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
| #define | ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
| #define | ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
| #define | ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
| #define | ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
| #define | ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
| #define | ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
| #define | ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
| #define | ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
| #define | ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
| #define | ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
| #define | ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
| #define | ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
| #define | ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
| #define | ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
| #define | ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
| #define | ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
| #define | ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
| #define | ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
| #define | ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
| #define | ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
| #define | ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
| #define | ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
| #define | ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| #define | ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| #define | ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| #define | ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| #define | ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| #define | ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
| #define | ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
| #define | ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
| #define | ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
| #define | ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| #define | ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
| #define | ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
| #define | ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
| #define | ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
| #define | ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
| #define | ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
| #define | ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
| #define | ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
| #define | ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
| #define | ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
| #define | ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
| #define | ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
| #define | ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
| #define | ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
| #define | ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
| #define | ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
| #define | ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
| #define | ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
| #define | ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
| #define | ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
| #define | ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
| #define | ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
| #define | ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
| #define | ADC_SR_AWD ((uint8_t)0x01) |
| #define | ADC_SR_EOC ((uint8_t)0x02) |
| #define | ADC_SR_JEOC ((uint8_t)0x04) |
| #define | ADC_SR_JSTRT ((uint8_t)0x08) |
| #define | ADC_SR_STRT ((uint8_t)0x10) |
| #define | ADC_SR_OVR ((uint8_t)0x20) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR1_RES ((uint32_t)0x03000000) |
| #define | ADC_CR1_RES_0 ((uint32_t)0x01000000) |
| #define | ADC_CR1_RES_1 ((uint32_t)0x02000000) |
| #define | ADC_CR1_OVRIE ((uint32_t)0x04000000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_DDS ((uint32_t)0x00000200) |
| #define | ADC_CR2_EOCS ((uint32_t)0x00000400) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) |
| #define | ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) |
| #define | ADC_CR2_JEXTEN ((uint32_t)0x00300000) |
| #define | ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) |
| #define | ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x0F000000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) |
| #define | ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) |
| #define | ADC_CR2_EXTEN ((uint32_t)0x30000000) |
| #define | ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) |
| #define | ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x40000000) |
| #define | ADC_SMPR1_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP18 ((uint32_t)0x07000000) |
| #define | ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) |
| #define | ADC_HTR_HT ((uint16_t)0x0FFF) |
| #define | ADC_LTR_LT ((uint16_t)0x0FFF) |
| #define | ADC_SQR1_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR1_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR2_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR3_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_JDR4_JDATA ((uint16_t)0xFFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) |
| #define | ADC_CSR_AWD1 ((uint32_t)0x00000001) |
| #define | ADC_CSR_EOC1 ((uint32_t)0x00000002) |
| #define | ADC_CSR_JEOC1 ((uint32_t)0x00000004) |
| #define | ADC_CSR_JSTRT1 ((uint32_t)0x00000008) |
| #define | ADC_CSR_STRT1 ((uint32_t)0x00000010) |
| #define | ADC_CSR_DOVR1 ((uint32_t)0x00000020) |
| #define | ADC_CSR_AWD2 ((uint32_t)0x00000100) |
| #define | ADC_CSR_EOC2 ((uint32_t)0x00000200) |
| #define | ADC_CSR_JEOC2 ((uint32_t)0x00000400) |
| #define | ADC_CSR_JSTRT2 ((uint32_t)0x00000800) |
| #define | ADC_CSR_STRT2 ((uint32_t)0x00001000) |
| #define | ADC_CSR_DOVR2 ((uint32_t)0x00002000) |
| #define | ADC_CSR_AWD3 ((uint32_t)0x00010000) |
| #define | ADC_CSR_EOC3 ((uint32_t)0x00020000) |
| #define | ADC_CSR_JEOC3 ((uint32_t)0x00040000) |
| #define | ADC_CSR_JSTRT3 ((uint32_t)0x00080000) |
| #define | ADC_CSR_STRT3 ((uint32_t)0x00100000) |
| #define | ADC_CSR_DOVR3 ((uint32_t)0x00200000) |
| #define | ADC_CCR_MULTI ((uint32_t)0x0000001F) |
| #define | ADC_CCR_MULTI_0 ((uint32_t)0x00000001) |
| #define | ADC_CCR_MULTI_1 ((uint32_t)0x00000002) |
| #define | ADC_CCR_MULTI_2 ((uint32_t)0x00000004) |
| #define | ADC_CCR_MULTI_3 ((uint32_t)0x00000008) |
| #define | ADC_CCR_MULTI_4 ((uint32_t)0x00000010) |
| #define | ADC_CCR_DELAY ((uint32_t)0x00000F00) |
| #define | ADC_CCR_DELAY_0 ((uint32_t)0x00000100) |
| #define | ADC_CCR_DELAY_1 ((uint32_t)0x00000200) |
| #define | ADC_CCR_DELAY_2 ((uint32_t)0x00000400) |
| #define | ADC_CCR_DELAY_3 ((uint32_t)0x00000800) |
| #define | ADC_CCR_DDS ((uint32_t)0x00002000) |
| #define | ADC_CCR_DMA ((uint32_t)0x0000C000) |
| #define | ADC_CCR_DMA_0 ((uint32_t)0x00004000) |
| #define | ADC_CCR_DMA_1 ((uint32_t)0x00008000) |
| #define | ADC_CCR_ADCPRE ((uint32_t)0x00030000) |
| #define | ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) |
| #define | ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) |
| #define | ADC_CCR_VBATE ((uint32_t)0x00400000) |
| #define | ADC_CCR_TSVREFE ((uint32_t)0x00800000) |
| #define | ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) |
| #define | ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) |
| #define | CAN_MCR_INRQ ((uint16_t)0x0001) |
| #define | CAN_MCR_SLEEP ((uint16_t)0x0002) |
| #define | CAN_MCR_TXFP ((uint16_t)0x0004) |
| #define | CAN_MCR_RFLM ((uint16_t)0x0008) |
| #define | CAN_MCR_NART ((uint16_t)0x0010) |
| #define | CAN_MCR_AWUM ((uint16_t)0x0020) |
| #define | CAN_MCR_ABOM ((uint16_t)0x0040) |
| #define | CAN_MCR_TTCM ((uint16_t)0x0080) |
| #define | CAN_MCR_RESET ((uint16_t)0x8000) |
| #define | CAN_MSR_INAK ((uint16_t)0x0001) |
| #define | CAN_MSR_SLAK ((uint16_t)0x0002) |
| #define | CAN_MSR_ERRI ((uint16_t)0x0004) |
| #define | CAN_MSR_WKUI ((uint16_t)0x0008) |
| #define | CAN_MSR_SLAKI ((uint16_t)0x0010) |
| #define | CAN_MSR_TXM ((uint16_t)0x0100) |
| #define | CAN_MSR_RXM ((uint16_t)0x0200) |
| #define | CAN_MSR_SAMP ((uint16_t)0x0400) |
| #define | CAN_MSR_RX ((uint16_t)0x0800) |
| #define | CAN_TSR_RQCP0 ((uint32_t)0x00000001) |
| #define | CAN_TSR_TXOK0 ((uint32_t)0x00000002) |
| #define | CAN_TSR_ALST0 ((uint32_t)0x00000004) |
| #define | CAN_TSR_TERR0 ((uint32_t)0x00000008) |
| #define | CAN_TSR_ABRQ0 ((uint32_t)0x00000080) |
| #define | CAN_TSR_RQCP1 ((uint32_t)0x00000100) |
| #define | CAN_TSR_TXOK1 ((uint32_t)0x00000200) |
| #define | CAN_TSR_ALST1 ((uint32_t)0x00000400) |
| #define | CAN_TSR_TERR1 ((uint32_t)0x00000800) |
| #define | CAN_TSR_ABRQ1 ((uint32_t)0x00008000) |
| #define | CAN_TSR_RQCP2 ((uint32_t)0x00010000) |
| #define | CAN_TSR_TXOK2 ((uint32_t)0x00020000) |
| #define | CAN_TSR_ALST2 ((uint32_t)0x00040000) |
| #define | CAN_TSR_TERR2 ((uint32_t)0x00080000) |
| #define | CAN_TSR_ABRQ2 ((uint32_t)0x00800000) |
| #define | CAN_TSR_CODE ((uint32_t)0x03000000) |
| #define | CAN_TSR_TME ((uint32_t)0x1C000000) |
| #define | CAN_TSR_TME0 ((uint32_t)0x04000000) |
| #define | CAN_TSR_TME1 ((uint32_t)0x08000000) |
| #define | CAN_TSR_TME2 ((uint32_t)0x10000000) |
| #define | CAN_TSR_LOW ((uint32_t)0xE0000000) |
| #define | CAN_TSR_LOW0 ((uint32_t)0x20000000) |
| #define | CAN_TSR_LOW1 ((uint32_t)0x40000000) |
| #define | CAN_TSR_LOW2 ((uint32_t)0x80000000) |
| #define | CAN_RF0R_FMP0 ((uint8_t)0x03) |
| #define | CAN_RF0R_FULL0 ((uint8_t)0x08) |
| #define | CAN_RF0R_FOVR0 ((uint8_t)0x10) |
| #define | CAN_RF0R_RFOM0 ((uint8_t)0x20) |
| #define | CAN_RF1R_FMP1 ((uint8_t)0x03) |
| #define | CAN_RF1R_FULL1 ((uint8_t)0x08) |
| #define | CAN_RF1R_FOVR1 ((uint8_t)0x10) |
| #define | CAN_RF1R_RFOM1 ((uint8_t)0x20) |
| #define | CAN_IER_TMEIE ((uint32_t)0x00000001) |
| #define | CAN_IER_FMPIE0 ((uint32_t)0x00000002) |
| #define | CAN_IER_FFIE0 ((uint32_t)0x00000004) |
| #define | CAN_IER_FOVIE0 ((uint32_t)0x00000008) |
| #define | CAN_IER_FMPIE1 ((uint32_t)0x00000010) |
| #define | CAN_IER_FFIE1 ((uint32_t)0x00000020) |
| #define | CAN_IER_FOVIE1 ((uint32_t)0x00000040) |
| #define | CAN_IER_EWGIE ((uint32_t)0x00000100) |
| #define | CAN_IER_EPVIE ((uint32_t)0x00000200) |
| #define | CAN_IER_BOFIE ((uint32_t)0x00000400) |
| #define | CAN_IER_LECIE ((uint32_t)0x00000800) |
| #define | CAN_IER_ERRIE ((uint32_t)0x00008000) |
| #define | CAN_IER_WKUIE ((uint32_t)0x00010000) |
| #define | CAN_IER_SLKIE ((uint32_t)0x00020000) |
| #define | CAN_ESR_EWGF ((uint32_t)0x00000001) |
| #define | CAN_ESR_EPVF ((uint32_t)0x00000002) |
| #define | CAN_ESR_BOFF ((uint32_t)0x00000004) |
| #define | CAN_ESR_LEC ((uint32_t)0x00000070) |
| #define | CAN_ESR_LEC_0 ((uint32_t)0x00000010) |
| #define | CAN_ESR_LEC_1 ((uint32_t)0x00000020) |
| #define | CAN_ESR_LEC_2 ((uint32_t)0x00000040) |
| #define | CAN_ESR_TEC ((uint32_t)0x00FF0000) |
| #define | CAN_ESR_REC ((uint32_t)0xFF000000) |
| #define | CAN_BTR_BRP ((uint32_t)0x000003FF) |
| #define | CAN_BTR_TS1 ((uint32_t)0x000F0000) |
| #define | CAN_BTR_TS2 ((uint32_t)0x00700000) |
| #define | CAN_BTR_SJW ((uint32_t)0x03000000) |
| #define | CAN_BTR_LBKM ((uint32_t)0x40000000) |
| #define | CAN_BTR_SILM ((uint32_t)0x80000000) |
| #define | CAN_TI0R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT0R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI1R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT1R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_TI2R_TXRQ ((uint32_t)0x00000001) |
| #define | CAN_TI2R_RTR ((uint32_t)0x00000002) |
| #define | CAN_TI2R_IDE ((uint32_t)0x00000004) |
| #define | CAN_TI2R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_TI2R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_TDT2R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_TDT2R_TGT ((uint32_t)0x00000100) |
| #define | CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI0R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI0R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI0R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI0R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT0R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT0R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_RI1R_RTR ((uint32_t)0x00000002) |
| #define | CAN_RI1R_IDE ((uint32_t)0x00000004) |
| #define | CAN_RI1R_EXID ((uint32_t)0x001FFFF8) |
| #define | CAN_RI1R_STID ((uint32_t)0xFFE00000) |
| #define | CAN_RDT1R_DLC ((uint32_t)0x0000000F) |
| #define | CAN_RDT1R_FMI ((uint32_t)0x0000FF00) |
| #define | CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) |
| #define | CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) |
| #define | CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) |
| #define | CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) |
| #define | CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) |
| #define | CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) |
| #define | CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) |
| #define | CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) |
| #define | CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) |
| #define | CAN_FMR_FINIT ((uint8_t)0x01) |
| #define | CAN_FM1R_FBM ((uint16_t)0x3FFF) |
| #define | CAN_FM1R_FBM0 ((uint16_t)0x0001) |
| #define | CAN_FM1R_FBM1 ((uint16_t)0x0002) |
| #define | CAN_FM1R_FBM2 ((uint16_t)0x0004) |
| #define | CAN_FM1R_FBM3 ((uint16_t)0x0008) |
| #define | CAN_FM1R_FBM4 ((uint16_t)0x0010) |
| #define | CAN_FM1R_FBM5 ((uint16_t)0x0020) |
| #define | CAN_FM1R_FBM6 ((uint16_t)0x0040) |
| #define | CAN_FM1R_FBM7 ((uint16_t)0x0080) |
| #define | CAN_FM1R_FBM8 ((uint16_t)0x0100) |
| #define | CAN_FM1R_FBM9 ((uint16_t)0x0200) |
| #define | CAN_FM1R_FBM10 ((uint16_t)0x0400) |
| #define | CAN_FM1R_FBM11 ((uint16_t)0x0800) |
| #define | CAN_FM1R_FBM12 ((uint16_t)0x1000) |
| #define | CAN_FM1R_FBM13 ((uint16_t)0x2000) |
| #define | CAN_FS1R_FSC ((uint16_t)0x3FFF) |
| #define | CAN_FS1R_FSC0 ((uint16_t)0x0001) |
| #define | CAN_FS1R_FSC1 ((uint16_t)0x0002) |
| #define | CAN_FS1R_FSC2 ((uint16_t)0x0004) |
| #define | CAN_FS1R_FSC3 ((uint16_t)0x0008) |
| #define | CAN_FS1R_FSC4 ((uint16_t)0x0010) |
| #define | CAN_FS1R_FSC5 ((uint16_t)0x0020) |
| #define | CAN_FS1R_FSC6 ((uint16_t)0x0040) |
| #define | CAN_FS1R_FSC7 ((uint16_t)0x0080) |
| #define | CAN_FS1R_FSC8 ((uint16_t)0x0100) |
| #define | CAN_FS1R_FSC9 ((uint16_t)0x0200) |
| #define | CAN_FS1R_FSC10 ((uint16_t)0x0400) |
| #define | CAN_FS1R_FSC11 ((uint16_t)0x0800) |
| #define | CAN_FS1R_FSC12 ((uint16_t)0x1000) |
| #define | CAN_FS1R_FSC13 ((uint16_t)0x2000) |
| #define | CAN_FFA1R_FFA ((uint16_t)0x3FFF) |
| #define | CAN_FFA1R_FFA0 ((uint16_t)0x0001) |
| #define | CAN_FFA1R_FFA1 ((uint16_t)0x0002) |
| #define | CAN_FFA1R_FFA2 ((uint16_t)0x0004) |
| #define | CAN_FFA1R_FFA3 ((uint16_t)0x0008) |
| #define | CAN_FFA1R_FFA4 ((uint16_t)0x0010) |
| #define | CAN_FFA1R_FFA5 ((uint16_t)0x0020) |
| #define | CAN_FFA1R_FFA6 ((uint16_t)0x0040) |
| #define | CAN_FFA1R_FFA7 ((uint16_t)0x0080) |
| #define | CAN_FFA1R_FFA8 ((uint16_t)0x0100) |
| #define | CAN_FFA1R_FFA9 ((uint16_t)0x0200) |
| #define | CAN_FFA1R_FFA10 ((uint16_t)0x0400) |
| #define | CAN_FFA1R_FFA11 ((uint16_t)0x0800) |
| #define | CAN_FFA1R_FFA12 ((uint16_t)0x1000) |
| #define | CAN_FFA1R_FFA13 ((uint16_t)0x2000) |
| #define | CAN_FA1R_FACT ((uint16_t)0x3FFF) |
| #define | CAN_FA1R_FACT0 ((uint16_t)0x0001) |
| #define | CAN_FA1R_FACT1 ((uint16_t)0x0002) |
| #define | CAN_FA1R_FACT2 ((uint16_t)0x0004) |
| #define | CAN_FA1R_FACT3 ((uint16_t)0x0008) |
| #define | CAN_FA1R_FACT4 ((uint16_t)0x0010) |
| #define | CAN_FA1R_FACT5 ((uint16_t)0x0020) |
| #define | CAN_FA1R_FACT6 ((uint16_t)0x0040) |
| #define | CAN_FA1R_FACT7 ((uint16_t)0x0080) |
| #define | CAN_FA1R_FACT8 ((uint16_t)0x0100) |
| #define | CAN_FA1R_FACT9 ((uint16_t)0x0200) |
| #define | CAN_FA1R_FACT10 ((uint16_t)0x0400) |
| #define | CAN_FA1R_FACT11 ((uint16_t)0x0800) |
| #define | CAN_FA1R_FACT12 ((uint16_t)0x1000) |
| #define | CAN_FA1R_FACT13 ((uint16_t)0x2000) |
| #define | CAN_F0R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R1_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R1_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R1_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R1_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R1_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R1_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R1_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R1_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R1_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R1_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R1_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R1_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R1_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R1_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R1_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R1_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R1_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R1_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R1_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R1_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R1_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R1_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R1_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R1_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R1_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R1_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R1_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R1_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R1_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R1_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R1_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R1_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F0R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F0R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F0R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F0R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F0R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F0R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F0R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F0R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F0R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F0R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F0R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F0R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F0R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F0R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F0R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F0R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F0R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F0R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F0R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F0R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F0R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F0R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F0R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F0R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F0R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F0R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F0R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F0R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F0R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F0R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F0R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F0R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F1R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F1R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F1R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F1R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F1R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F1R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F1R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F1R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F1R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F1R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F1R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F1R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F1R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F1R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F1R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F1R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F1R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F1R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F1R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F1R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F1R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F1R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F1R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F1R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F1R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F1R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F1R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F1R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F1R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F1R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F1R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F1R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F2R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F2R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F2R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F2R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F2R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F2R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F2R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F2R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F2R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F2R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F2R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F2R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F2R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F2R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F2R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F2R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F2R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F2R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F2R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F2R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F2R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F2R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F2R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F2R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F2R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F2R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F2R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F2R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F2R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F2R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F2R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F2R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F3R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F3R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F3R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F3R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F3R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F3R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F3R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F3R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F3R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F3R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F3R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F3R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F3R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F3R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F3R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F3R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F3R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F3R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F3R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F3R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F3R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F3R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F3R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F3R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F3R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F3R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F3R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F3R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F3R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F3R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F3R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F3R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F4R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F4R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F4R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F4R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F4R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F4R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F4R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F4R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F4R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F4R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F4R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F4R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F4R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F4R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F4R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F4R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F4R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F4R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F4R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F4R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F4R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F4R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F4R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F4R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F4R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F4R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F4R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F4R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F4R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F4R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F4R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F4R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F5R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F5R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F5R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F5R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F5R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F5R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F5R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F5R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F5R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F5R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F5R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F5R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F5R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F5R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F5R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F5R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F5R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F5R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F5R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F5R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F5R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F5R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F5R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F5R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F5R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F5R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F5R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F5R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F5R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F5R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F5R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F5R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F6R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F6R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F6R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F6R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F6R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F6R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F6R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F6R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F6R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F6R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F6R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F6R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F6R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F6R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F6R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F6R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F6R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F6R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F6R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F6R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F6R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F6R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F6R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F6R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F6R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F6R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F6R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F6R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F6R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F6R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F6R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F6R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F7R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F7R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F7R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F7R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F7R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F7R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F7R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F7R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F7R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F7R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F7R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F7R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F7R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F7R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F7R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F7R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F7R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F7R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F7R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F7R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F7R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F7R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F7R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F7R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F7R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F7R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F7R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F7R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F7R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F7R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F7R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F7R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F8R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F8R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F8R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F8R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F8R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F8R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F8R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F8R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F8R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F8R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F8R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F8R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F8R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F8R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F8R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F8R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F8R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F8R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F8R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F8R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F8R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F8R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F8R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F8R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F8R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F8R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F8R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F8R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F8R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F8R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F8R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F8R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F9R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F9R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F9R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F9R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F9R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F9R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F9R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F9R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F9R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F9R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F9R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F9R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F9R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F9R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F9R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F9R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F9R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F9R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F9R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F9R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F9R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F9R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F9R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F9R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F9R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F9R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F9R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F9R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F9R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F9R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F9R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F9R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F10R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F10R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F10R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F10R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F10R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F10R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F10R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F10R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F10R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F10R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F10R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F10R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F10R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F10R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F10R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F10R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F10R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F10R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F10R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F10R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F10R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F10R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F10R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F10R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F10R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F10R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F10R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F10R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F10R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F10R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F10R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F10R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F11R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F11R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F11R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F11R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F11R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F11R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F11R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F11R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F11R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F11R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F11R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F11R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F11R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F11R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F11R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F11R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F11R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F11R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F11R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F11R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F11R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F11R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F11R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F11R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F11R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F11R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F11R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F11R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F11R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F11R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F11R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F11R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F12R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F12R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F12R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F12R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F12R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F12R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F12R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F12R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F12R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F12R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F12R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F12R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F12R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F12R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F12R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F12R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F12R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F12R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F12R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F12R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F12R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F12R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F12R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F12R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F12R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F12R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F12R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F12R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F12R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F12R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F12R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F12R2_FB31 ((uint32_t)0x80000000) |
| #define | CAN_F13R2_FB0 ((uint32_t)0x00000001) |
| #define | CAN_F13R2_FB1 ((uint32_t)0x00000002) |
| #define | CAN_F13R2_FB2 ((uint32_t)0x00000004) |
| #define | CAN_F13R2_FB3 ((uint32_t)0x00000008) |
| #define | CAN_F13R2_FB4 ((uint32_t)0x00000010) |
| #define | CAN_F13R2_FB5 ((uint32_t)0x00000020) |
| #define | CAN_F13R2_FB6 ((uint32_t)0x00000040) |
| #define | CAN_F13R2_FB7 ((uint32_t)0x00000080) |
| #define | CAN_F13R2_FB8 ((uint32_t)0x00000100) |
| #define | CAN_F13R2_FB9 ((uint32_t)0x00000200) |
| #define | CAN_F13R2_FB10 ((uint32_t)0x00000400) |
| #define | CAN_F13R2_FB11 ((uint32_t)0x00000800) |
| #define | CAN_F13R2_FB12 ((uint32_t)0x00001000) |
| #define | CAN_F13R2_FB13 ((uint32_t)0x00002000) |
| #define | CAN_F13R2_FB14 ((uint32_t)0x00004000) |
| #define | CAN_F13R2_FB15 ((uint32_t)0x00008000) |
| #define | CAN_F13R2_FB16 ((uint32_t)0x00010000) |
| #define | CAN_F13R2_FB17 ((uint32_t)0x00020000) |
| #define | CAN_F13R2_FB18 ((uint32_t)0x00040000) |
| #define | CAN_F13R2_FB19 ((uint32_t)0x00080000) |
| #define | CAN_F13R2_FB20 ((uint32_t)0x00100000) |
| #define | CAN_F13R2_FB21 ((uint32_t)0x00200000) |
| #define | CAN_F13R2_FB22 ((uint32_t)0x00400000) |
| #define | CAN_F13R2_FB23 ((uint32_t)0x00800000) |
| #define | CAN_F13R2_FB24 ((uint32_t)0x01000000) |
| #define | CAN_F13R2_FB25 ((uint32_t)0x02000000) |
| #define | CAN_F13R2_FB26 ((uint32_t)0x04000000) |
| #define | CAN_F13R2_FB27 ((uint32_t)0x08000000) |
| #define | CAN_F13R2_FB28 ((uint32_t)0x10000000) |
| #define | CAN_F13R2_FB29 ((uint32_t)0x20000000) |
| #define | CAN_F13R2_FB30 ((uint32_t)0x40000000) |
| #define | CAN_F13R2_FB31 ((uint32_t)0x80000000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint8_t)0x01) |
| #define | CRYP_CR_ALGODIR ((uint32_t)0x00000004) |
| #define | CRYP_CR_ALGOMODE ((uint32_t)0x00080038) |
| #define | CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) |
| #define | CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) |
| #define | CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) |
| #define | CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) |
| #define | CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) |
| #define | CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) |
| #define | CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) |
| #define | CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) |
| #define | CRYP_CR_DATATYPE ((uint32_t)0x000000C0) |
| #define | CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) |
| #define | CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) |
| #define | CRYP_CR_KEYSIZE ((uint32_t)0x00000300) |
| #define | CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) |
| #define | CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) |
| #define | CRYP_CR_FFLUSH ((uint32_t)0x00004000) |
| #define | CRYP_CR_CRYPEN ((uint32_t)0x00008000) |
| #define | CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000) |
| #define | CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000) |
| #define | CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000) |
| #define | CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) |
| #define | CRYP_SR_IFEM ((uint32_t)0x00000001) |
| #define | CRYP_SR_IFNF ((uint32_t)0x00000002) |
| #define | CRYP_SR_OFNE ((uint32_t)0x00000004) |
| #define | CRYP_SR_OFFU ((uint32_t)0x00000008) |
| #define | CRYP_SR_BUSY ((uint32_t)0x00000010) |
| #define | CRYP_DMACR_DIEN ((uint32_t)0x00000001) |
| #define | CRYP_DMACR_DOEN ((uint32_t)0x00000002) |
| #define | CRYP_IMSCR_INIM ((uint32_t)0x00000001) |
| #define | CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) |
| #define | CRYP_RISR_OUTRIS ((uint32_t)0x00000001) |
| #define | CRYP_RISR_INRIS ((uint32_t)0x00000002) |
| #define | CRYP_MISR_INMIS ((uint32_t)0x00000001) |
| #define | CRYP_MISR_OUTMIS ((uint32_t)0x00000002) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | DCMI_CR_CAPTURE ((uint32_t)0x00000001) |
| #define | DCMI_CR_CM ((uint32_t)0x00000002) |
| #define | DCMI_CR_CROP ((uint32_t)0x00000004) |
| #define | DCMI_CR_JPEG ((uint32_t)0x00000008) |
| #define | DCMI_CR_ESS ((uint32_t)0x00000010) |
| #define | DCMI_CR_PCKPOL ((uint32_t)0x00000020) |
| #define | DCMI_CR_HSPOL ((uint32_t)0x00000040) |
| #define | DCMI_CR_VSPOL ((uint32_t)0x00000080) |
| #define | DCMI_CR_FCRC_0 ((uint32_t)0x00000100) |
| #define | DCMI_CR_FCRC_1 ((uint32_t)0x00000200) |
| #define | DCMI_CR_EDM_0 ((uint32_t)0x00000400) |
| #define | DCMI_CR_EDM_1 ((uint32_t)0x00000800) |
| #define | DCMI_CR_CRE ((uint32_t)0x00001000) |
| #define | DCMI_CR_ENABLE ((uint32_t)0x00004000) |
| #define | DCMI_SR_HSYNC ((uint32_t)0x00000001) |
| #define | DCMI_SR_VSYNC ((uint32_t)0x00000002) |
| #define | DCMI_SR_FNE ((uint32_t)0x00000004) |
| #define | DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) |
| #define | DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) |
| #define | DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) |
| #define | DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) |
| #define | DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) |
| #define | DCMI_IER_FRAME_IE ((uint32_t)0x00000001) |
| #define | DCMI_IER_OVF_IE ((uint32_t)0x00000002) |
| #define | DCMI_IER_ERR_IE ((uint32_t)0x00000004) |
| #define | DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) |
| #define | DCMI_IER_LINE_IE ((uint32_t)0x00000010) |
| #define | DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) |
| #define | DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) |
| #define | DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) |
| #define | DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) |
| #define | DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) |
| #define | DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) |
| #define | DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) |
| #define | DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) |
| #define | DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) |
| #define | DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) |
| #define | DMA_SxCR_CHSEL ((uint32_t)0x0E000000) |
| #define | DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) |
| #define | DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) |
| #define | DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) |
| #define | DMA_SxCR_MBURST ((uint32_t)0x01800000) |
| #define | DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) |
| #define | DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) |
| #define | DMA_SxCR_PBURST ((uint32_t)0x00600000) |
| #define | DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) |
| #define | DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) |
| #define | DMA_SxCR_ACK ((uint32_t)0x00100000) |
| #define | DMA_SxCR_CT ((uint32_t)0x00080000) |
| #define | DMA_SxCR_DBM ((uint32_t)0x00040000) |
| #define | DMA_SxCR_PL ((uint32_t)0x00030000) |
| #define | DMA_SxCR_PL_0 ((uint32_t)0x00010000) |
| #define | DMA_SxCR_PL_1 ((uint32_t)0x00020000) |
| #define | DMA_SxCR_PINCOS ((uint32_t)0x00008000) |
| #define | DMA_SxCR_MSIZE ((uint32_t)0x00006000) |
| #define | DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) |
| #define | DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) |
| #define | DMA_SxCR_PSIZE ((uint32_t)0x00001800) |
| #define | DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) |
| #define | DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) |
| #define | DMA_SxCR_MINC ((uint32_t)0x00000400) |
| #define | DMA_SxCR_PINC ((uint32_t)0x00000200) |
| #define | DMA_SxCR_CIRC ((uint32_t)0x00000100) |
| #define | DMA_SxCR_DIR ((uint32_t)0x000000C0) |
| #define | DMA_SxCR_DIR_0 ((uint32_t)0x00000040) |
| #define | DMA_SxCR_DIR_1 ((uint32_t)0x00000080) |
| #define | DMA_SxCR_PFCTRL ((uint32_t)0x00000020) |
| #define | DMA_SxCR_TCIE ((uint32_t)0x00000010) |
| #define | DMA_SxCR_HTIE ((uint32_t)0x00000008) |
| #define | DMA_SxCR_TEIE ((uint32_t)0x00000004) |
| #define | DMA_SxCR_DMEIE ((uint32_t)0x00000002) |
| #define | DMA_SxCR_EN ((uint32_t)0x00000001) |
| #define | DMA_SxNDT ((uint32_t)0x0000FFFF) |
| #define | DMA_SxNDT_0 ((uint32_t)0x00000001) |
| #define | DMA_SxNDT_1 ((uint32_t)0x00000002) |
| #define | DMA_SxNDT_2 ((uint32_t)0x00000004) |
| #define | DMA_SxNDT_3 ((uint32_t)0x00000008) |
| #define | DMA_SxNDT_4 ((uint32_t)0x00000010) |
| #define | DMA_SxNDT_5 ((uint32_t)0x00000020) |
| #define | DMA_SxNDT_6 ((uint32_t)0x00000040) |
| #define | DMA_SxNDT_7 ((uint32_t)0x00000080) |
| #define | DMA_SxNDT_8 ((uint32_t)0x00000100) |
| #define | DMA_SxNDT_9 ((uint32_t)0x00000200) |
| #define | DMA_SxNDT_10 ((uint32_t)0x00000400) |
| #define | DMA_SxNDT_11 ((uint32_t)0x00000800) |
| #define | DMA_SxNDT_12 ((uint32_t)0x00001000) |
| #define | DMA_SxNDT_13 ((uint32_t)0x00002000) |
| #define | DMA_SxNDT_14 ((uint32_t)0x00004000) |
| #define | DMA_SxNDT_15 ((uint32_t)0x00008000) |
| #define | DMA_SxFCR_FEIE ((uint32_t)0x00000080) |
| #define | DMA_SxFCR_FS ((uint32_t)0x00000038) |
| #define | DMA_SxFCR_FS_0 ((uint32_t)0x00000008) |
| #define | DMA_SxFCR_FS_1 ((uint32_t)0x00000010) |
| #define | DMA_SxFCR_FS_2 ((uint32_t)0x00000020) |
| #define | DMA_SxFCR_DMDIS ((uint32_t)0x00000004) |
| #define | DMA_SxFCR_FTH ((uint32_t)0x00000003) |
| #define | DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) |
| #define | DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) |
| #define | DMA_LISR_TCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LISR_HTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LISR_TEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LISR_DMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LISR_FEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LISR_TCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LISR_HTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LISR_TEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LISR_DMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LISR_FEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LISR_TCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LISR_HTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LISR_TEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LISR_DMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LISR_FEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LISR_TCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LISR_HTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LISR_TEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LISR_DMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LISR_FEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HISR_TCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HISR_TEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HISR_DMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HISR_FEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HISR_HTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HISR_TEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HISR_DMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HISR_FEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HISR_TCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HISR_HTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HISR_TEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HISR_DMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HISR_FEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HISR_TCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HISR_HTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HISR_TEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HISR_DMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HISR_FEIF4 ((uint32_t)0x00000001) |
| #define | DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) |
| #define | DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) |
| #define | DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) |
| #define | DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) |
| #define | DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) |
| #define | DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) |
| #define | DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) |
| #define | DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) |
| #define | DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) |
| #define | DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) |
| #define | DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) |
| #define | DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) |
| #define | DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) |
| #define | DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) |
| #define | DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) |
| #define | DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) |
| #define | DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) |
| #define | DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) |
| #define | DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) |
| #define | DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) |
| #define | DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) |
| #define | DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) |
| #define | DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) |
| #define | DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) |
| #define | DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) |
| #define | DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) |
| #define | DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) |
| #define | DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) |
| #define | DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) |
| #define | DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) |
| #define | DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) |
| #define | DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) |
| #define | DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) |
| #define | DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) |
| #define | DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) |
| #define | DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) |
| #define | DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) |
| #define | DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) |
| #define | DMA2D_CR_START ((uint32_t)0x00000001) |
| #define | DMA2D_CR_SUSP ((uint32_t)0x00000002) |
| #define | DMA2D_CR_ABORT ((uint32_t)0x00000004) |
| #define | DMA2D_CR_TEIE ((uint32_t)0x00000100) |
| #define | DMA2D_CR_TCIE ((uint32_t)0x00000200) |
| #define | DMA2D_CR_TWIE ((uint32_t)0x00000400) |
| #define | DMA2D_CR_CAEIE ((uint32_t)0x00000800) |
| #define | DMA2D_CR_CTCIE ((uint32_t)0x00001000) |
| #define | DMA2D_CR_CEIE ((uint32_t)0x00002000) |
| #define | DMA2D_CR_MODE ((uint32_t)0x00030000) |
| #define | DMA2D_ISR_TEIF ((uint32_t)0x00000001) |
| #define | DMA2D_ISR_TCIF ((uint32_t)0x00000002) |
| #define | DMA2D_ISR_TWIF ((uint32_t)0x00000004) |
| #define | DMA2D_ISR_CAEIF ((uint32_t)0x00000008) |
| #define | DMA2D_ISR_CTCIF ((uint32_t)0x00000010) |
| #define | DMA2D_ISR_CEIF ((uint32_t)0x00000020) |
| #define | DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) |
| #define | DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) |
| #define | DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) |
| #define | DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) |
| #define | DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) |
| #define | DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) |
| #define | DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_FGOR_LO ((uint32_t)0x00003FFF) |
| #define | DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_BGOR_LO ((uint32_t)0x00003FFF) |
| #define | DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) |
| #define | DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) |
| #define | DMA2D_FGPFCCR_START ((uint32_t)0x00000020) |
| #define | DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) |
| #define | DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) |
| #define | DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) |
| #define | DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) |
| #define | DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) |
| #define | DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) |
| #define | DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) |
| #define | DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) |
| #define | DMA2D_BGPFCCR_START ((uint32_t)0x00000020) |
| #define | DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) |
| #define | DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) |
| #define | DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) |
| #define | DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) |
| #define | DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) |
| #define | DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) |
| #define | DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_OPFCCR_CM ((uint32_t)0x00000007) |
| #define | DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) |
| #define | DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) |
| #define | DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) |
| #define | DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) |
| #define | DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) |
| #define | DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) |
| #define | DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) |
| #define | DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) |
| #define | DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) |
| #define | DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) |
| #define | DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) |
| #define | DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) |
| #define | DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) |
| #define | DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) |
| #define | DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) |
| #define | DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA2D_OOR_LO ((uint32_t)0x00003FFF) |
| #define | DMA2D_NLR_NL ((uint32_t)0x0000FFFF) |
| #define | DMA2D_NLR_PL ((uint32_t)0x3FFF0000) |
| #define | DMA2D_LWR_LW ((uint32_t)0x0000FFFF) |
| #define | DMA2D_AMTCR_EN ((uint32_t)0x00000001) |
| #define | DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x0000000F) |
| #define | FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
| #define | FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
| #define | FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
| #define | FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
| #define | FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
| #define | FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) |
| #define | FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) |
| #define | FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) |
| #define | FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008) |
| #define | FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009) |
| #define | FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A) |
| #define | FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B) |
| #define | FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C) |
| #define | FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D) |
| #define | FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E) |
| #define | FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F) |
| #define | FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
| #define | FLASH_ACR_ICEN ((uint32_t)0x00000200) |
| #define | FLASH_ACR_DCEN ((uint32_t)0x00000400) |
| #define | FLASH_ACR_ICRST ((uint32_t)0x00000800) |
| #define | FLASH_ACR_DCRST ((uint32_t)0x00001000) |
| #define | FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) |
| #define | FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000001) |
| #define | FLASH_SR_SOP ((uint32_t)0x00000002) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| #define | FLASH_SR_PGAERR ((uint32_t)0x00000020) |
| #define | FLASH_SR_PGPERR ((uint32_t)0x00000040) |
| #define | FLASH_SR_PGSERR ((uint32_t)0x00000080) |
| #define | FLASH_SR_BSY ((uint32_t)0x00010000) |
| #define | FLASH_CR_PG ((uint32_t)0x00000001) |
| #define | FLASH_CR_SER ((uint32_t)0x00000002) |
| #define | FLASH_CR_MER ((uint32_t)0x00000004) |
| #define | FLASH_CR_MER1 FLASH_CR_MER |
| #define | FLASH_CR_SNB ((uint32_t)0x000000F8) |
| #define | FLASH_CR_SNB_0 ((uint32_t)0x00000008) |
| #define | FLASH_CR_SNB_1 ((uint32_t)0x00000010) |
| #define | FLASH_CR_SNB_2 ((uint32_t)0x00000020) |
| #define | FLASH_CR_SNB_3 ((uint32_t)0x00000040) |
| #define | FLASH_CR_SNB_4 ((uint32_t)0x00000040) |
| #define | FLASH_CR_PSIZE ((uint32_t)0x00000300) |
| #define | FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) |
| #define | FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) |
| #define | FLASH_CR_MER2 ((uint32_t)0x00008000) |
| #define | FLASH_CR_STRT ((uint32_t)0x00010000) |
| #define | FLASH_CR_EOPIE ((uint32_t)0x01000000) |
| #define | FLASH_CR_LOCK ((uint32_t)0x80000000) |
| #define | FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) |
| #define | FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) |
| #define | FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) |
| #define | FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) |
| #define | FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) |
| #define | FLASH_OPTCR_BFB2 ((uint32_t)0x00000010) |
| #define | FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) |
| #define | FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) |
| #define | FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) |
| #define | FLASH_OPTCR_RDP ((uint32_t)0x0000FF00) |
| #define | FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) |
| #define | FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) |
| #define | FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) |
| #define | FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) |
| #define | FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) |
| #define | FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) |
| #define | FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) |
| #define | FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) |
| #define | FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000) |
| #define | FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) |
| #define | FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) |
| #define | FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) |
| #define | FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) |
| #define | FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) |
| #define | FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) |
| #define | FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) |
| #define | FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) |
| #define | FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) |
| #define | FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) |
| #define | FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) |
| #define | FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) |
| #define | FLASH_OPTCR_DB1M ((uint32_t)0x40000000) |
| #define | FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000) |
| #define | FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000) |
| #define | FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000) |
| #define | FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000) |
| #define | FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000) |
| #define | FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000) |
| #define | FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000) |
| #define | FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000) |
| #define | FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000) |
| #define | FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000) |
| #define | FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000) |
| #define | FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000) |
| #define | FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000) |
| #define | FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
| #define | GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
| #define | GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
| #define | GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
| #define | GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
| #define | GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
| #define | GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
| #define | GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
| #define | GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
| #define | GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
| #define | GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
| #define | GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
| #define | GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
| #define | GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
| #define | GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
| #define | GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
| #define | GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
| #define | GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
| #define | GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
| #define | GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
| #define | GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
| #define | GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
| #define | GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
| #define | GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
| #define | GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
| #define | GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
| #define | GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
| #define | GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
| #define | GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
| #define | GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
| #define | GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
| #define | GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | HASH_CR_INIT ((uint32_t)0x00000004) |
| #define | HASH_CR_DMAE ((uint32_t)0x00000008) |
| #define | HASH_CR_DATATYPE ((uint32_t)0x00000030) |
| #define | HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) |
| #define | HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) |
| #define | HASH_CR_MODE ((uint32_t)0x00000040) |
| #define | HASH_CR_ALGO ((uint32_t)0x00040080) |
| #define | HASH_CR_ALGO_0 ((uint32_t)0x00000080) |
| #define | HASH_CR_ALGO_1 ((uint32_t)0x00040000) |
| #define | HASH_CR_NBW ((uint32_t)0x00000F00) |
| #define | HASH_CR_NBW_0 ((uint32_t)0x00000100) |
| #define | HASH_CR_NBW_1 ((uint32_t)0x00000200) |
| #define | HASH_CR_NBW_2 ((uint32_t)0x00000400) |
| #define | HASH_CR_NBW_3 ((uint32_t)0x00000800) |
| #define | HASH_CR_DINNE ((uint32_t)0x00001000) |
| #define | HASH_CR_MDMAT ((uint32_t)0x00002000) |
| #define | HASH_CR_LKEY ((uint32_t)0x00010000) |
| #define | HASH_STR_NBW ((uint32_t)0x0000001F) |
| #define | HASH_STR_NBW_0 ((uint32_t)0x00000001) |
| #define | HASH_STR_NBW_1 ((uint32_t)0x00000002) |
| #define | HASH_STR_NBW_2 ((uint32_t)0x00000004) |
| #define | HASH_STR_NBW_3 ((uint32_t)0x00000008) |
| #define | HASH_STR_NBW_4 ((uint32_t)0x00000010) |
| #define | HASH_STR_DCAL ((uint32_t)0x00000100) |
| #define | HASH_IMR_DINIM ((uint32_t)0x00000001) |
| #define | HASH_IMR_DCIM ((uint32_t)0x00000002) |
| #define | HASH_SR_DINIS ((uint32_t)0x00000001) |
| #define | HASH_SR_DCIS ((uint32_t)0x00000002) |
| #define | HASH_SR_DMAS ((uint32_t)0x00000004) |
| #define | HASH_SR_BUSY ((uint32_t)0x00000008) |
| #define | I2C_CR1_PE ((uint16_t)0x0001) |
| #define | I2C_CR1_SMBUS ((uint16_t)0x0002) |
| #define | I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
| #define | I2C_CR1_ENARP ((uint16_t)0x0010) |
| #define | I2C_CR1_ENPEC ((uint16_t)0x0020) |
| #define | I2C_CR1_ENGC ((uint16_t)0x0040) |
| #define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
| #define | I2C_CR1_START ((uint16_t)0x0100) |
| #define | I2C_CR1_STOP ((uint16_t)0x0200) |
| #define | I2C_CR1_ACK ((uint16_t)0x0400) |
| #define | I2C_CR1_POS ((uint16_t)0x0800) |
| #define | I2C_CR1_PEC ((uint16_t)0x1000) |
| #define | I2C_CR1_ALERT ((uint16_t)0x2000) |
| #define | I2C_CR1_SWRST ((uint16_t)0x8000) |
| #define | I2C_CR2_FREQ ((uint16_t)0x003F) |
| #define | I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
| #define | I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
| #define | I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
| #define | I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
| #define | I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
| #define | I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
| #define | I2C_CR2_ITERREN ((uint16_t)0x0100) |
| #define | I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
| #define | I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
| #define | I2C_CR2_DMAEN ((uint16_t)0x0800) |
| #define | I2C_CR2_LAST ((uint16_t)0x1000) |
| #define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
| #define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
| #define | I2C_OAR1_ADD0 ((uint16_t)0x0001) |
| #define | I2C_OAR1_ADD1 ((uint16_t)0x0002) |
| #define | I2C_OAR1_ADD2 ((uint16_t)0x0004) |
| #define | I2C_OAR1_ADD3 ((uint16_t)0x0008) |
| #define | I2C_OAR1_ADD4 ((uint16_t)0x0010) |
| #define | I2C_OAR1_ADD5 ((uint16_t)0x0020) |
| #define | I2C_OAR1_ADD6 ((uint16_t)0x0040) |
| #define | I2C_OAR1_ADD7 ((uint16_t)0x0080) |
| #define | I2C_OAR1_ADD8 ((uint16_t)0x0100) |
| #define | I2C_OAR1_ADD9 ((uint16_t)0x0200) |
| #define | I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
| #define | I2C_OAR2_ENDUAL ((uint8_t)0x01) |
| #define | I2C_OAR2_ADD2 ((uint8_t)0xFE) |
| #define | I2C_DR_DR ((uint8_t)0xFF) |
| #define | I2C_SR1_SB ((uint16_t)0x0001) |
| #define | I2C_SR1_ADDR ((uint16_t)0x0002) |
| #define | I2C_SR1_BTF ((uint16_t)0x0004) |
| #define | I2C_SR1_ADD10 ((uint16_t)0x0008) |
| #define | I2C_SR1_STOPF ((uint16_t)0x0010) |
| #define | I2C_SR1_RXNE ((uint16_t)0x0040) |
| #define | I2C_SR1_TXE ((uint16_t)0x0080) |
| #define | I2C_SR1_BERR ((uint16_t)0x0100) |
| #define | I2C_SR1_ARLO ((uint16_t)0x0200) |
| #define | I2C_SR1_AF ((uint16_t)0x0400) |
| #define | I2C_SR1_OVR ((uint16_t)0x0800) |
| #define | I2C_SR1_PECERR ((uint16_t)0x1000) |
| #define | I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
| #define | I2C_SR1_SMBALERT ((uint16_t)0x8000) |
| #define | I2C_SR2_MSL ((uint16_t)0x0001) |
| #define | I2C_SR2_BUSY ((uint16_t)0x0002) |
| #define | I2C_SR2_TRA ((uint16_t)0x0004) |
| #define | I2C_SR2_GENCALL ((uint16_t)0x0010) |
| #define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
| #define | I2C_SR2_SMBHOST ((uint16_t)0x0040) |
| #define | I2C_SR2_DUALF ((uint16_t)0x0080) |
| #define | I2C_SR2_PEC ((uint16_t)0xFF00) |
| #define | I2C_CCR_CCR ((uint16_t)0x0FFF) |
| #define | I2C_CCR_DUTY ((uint16_t)0x4000) |
| #define | I2C_CCR_FS ((uint16_t)0x8000) |
| #define | I2C_TRISE_TRISE ((uint8_t)0x3F) |
| #define | I2C_FLTR_DNF ((uint8_t)0x0F) |
| #define | I2C_FLTR_ANOFF ((uint8_t)0x10) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | LTDC_SSCR_VSH ((uint32_t)0x000007FF) |
| #define | LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) |
| #define | LTDC_BPCR_AVBP ((uint32_t)0x000007FF) |
| #define | LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) |
| #define | LTDC_AWCR_AAH ((uint32_t)0x000007FF) |
| #define | LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) |
| #define | LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) |
| #define | LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) |
| #define | LTDC_GCR_LTDCEN ((uint32_t)0x00000001) |
| #define | LTDC_GCR_DBW ((uint32_t)0x00000070) |
| #define | LTDC_GCR_DGW ((uint32_t)0x00000700) |
| #define | LTDC_GCR_DRW ((uint32_t)0x00007000) |
| #define | LTDC_GCR_DTEN ((uint32_t)0x00010000) |
| #define | LTDC_GCR_PCPOL ((uint32_t)0x10000000) |
| #define | LTDC_GCR_DEPOL ((uint32_t)0x20000000) |
| #define | LTDC_GCR_VSPOL ((uint32_t)0x40000000) |
| #define | LTDC_GCR_HSPOL ((uint32_t)0x80000000) |
| #define | LTDC_SRCR_IMR ((uint32_t)0x00000001) |
| #define | LTDC_SRCR_VBR ((uint32_t)0x00000002) |
| #define | LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) |
| #define | LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) |
| #define | LTDC_IER_LIE ((uint32_t)0x00000001) |
| #define | LTDC_IER_FUIE ((uint32_t)0x00000002) |
| #define | LTDC_IER_TERRIE ((uint32_t)0x00000004) |
| #define | LTDC_IER_RRIE ((uint32_t)0x00000008) |
| #define | LTDC_ISR_LIF ((uint32_t)0x00000001) |
| #define | LTDC_ISR_FUIF ((uint32_t)0x00000002) |
| #define | LTDC_ISR_TERRIF ((uint32_t)0x00000004) |
| #define | LTDC_ISR_RRIF ((uint32_t)0x00000008) |
| #define | LTDC_ICR_CLIF ((uint32_t)0x00000001) |
| #define | LTDC_ICR_CFUIF ((uint32_t)0x00000002) |
| #define | LTDC_ICR_CTERRIF ((uint32_t)0x00000004) |
| #define | LTDC_ICR_CRRIF ((uint32_t)0x00000008) |
| #define | LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) |
| #define | LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) |
| #define | LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) |
| #define | LTDC_CDSR_VDES ((uint32_t)0x00000001) |
| #define | LTDC_CDSR_HDES ((uint32_t)0x00000002) |
| #define | LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) |
| #define | LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) |
| #define | LTDC_LxCR_LEN ((uint32_t)0x00000001) |
| #define | LTDC_LxCR_COLKEN ((uint32_t)0x00000002) |
| #define | LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) |
| #define | LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) |
| #define | LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) |
| #define | LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) |
| #define | LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) |
| #define | LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) |
| #define | LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) |
| #define | LTDC_LxPFCR_PF ((uint32_t)0x00000007) |
| #define | LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) |
| #define | LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) |
| #define | LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) |
| #define | LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) |
| #define | LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) |
| #define | LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) |
| #define | LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) |
| #define | LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) |
| #define | LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) |
| #define | LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) |
| #define | LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) |
| #define | LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) |
| #define | LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) |
| #define | LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) |
| #define | PWR_CR_LPDS ((uint32_t)0x00000001) |
| #define | PWR_CR_PDDS ((uint32_t)0x00000002) |
| #define | PWR_CR_CWUF ((uint32_t)0x00000004) |
| #define | PWR_CR_CSBF ((uint32_t)0x00000008) |
| #define | PWR_CR_PVDE ((uint32_t)0x00000010) |
| #define | PWR_CR_PLS ((uint32_t)0x000000E0) |
| #define | PWR_CR_PLS_0 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_1 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_2 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) |
| #define | PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) |
| #define | PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) |
| #define | PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) |
| #define | PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) |
| #define | PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) |
| #define | PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) |
| #define | PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) |
| #define | PWR_CR_DBP ((uint32_t)0x00000100) |
| #define | PWR_CR_FPDS ((uint32_t)0x00000200) |
| #define | PWR_CR_LPUDS ((uint32_t)0x00000400) |
| #define | PWR_CR_MRUDS ((uint32_t)0x00000800) |
| #define | PWR_CR_ADCDC1 ((uint32_t)0x00002000) |
| #define | PWR_CR_VOS ((uint32_t)0x0000C000) |
| #define | PWR_CR_VOS_0 ((uint32_t)0x00004000) |
| #define | PWR_CR_VOS_1 ((uint32_t)0x00008000) |
| #define | PWR_CR_ODEN ((uint32_t)0x00010000) |
| #define | PWR_CR_ODSWEN ((uint32_t)0x00020000) |
| #define | PWR_CR_UDEN ((uint32_t)0x000C0000) |
| #define | PWR_CR_UDEN_0 ((uint32_t)0x00040000) |
| #define | PWR_CR_UDEN_1 ((uint32_t)0x00080000) |
| #define | PWR_CR_PMODE PWR_CR_VOS |
| #define | PWR_CSR_WUF ((uint32_t)0x00000001) |
| #define | PWR_CSR_SBF ((uint32_t)0x00000002) |
| #define | PWR_CSR_PVDO ((uint32_t)0x00000004) |
| #define | PWR_CSR_BRR ((uint32_t)0x00000008) |
| #define | PWR_CSR_EWUP ((uint32_t)0x00000100) |
| #define | PWR_CSR_BRE ((uint32_t)0x00000200) |
| #define | PWR_CSR_VOSRDY ((uint32_t)0x00004000) |
| #define | PWR_CSR_ODRDY ((uint32_t)0x00010000) |
| #define | PWR_CSR_ODSWRDY ((uint32_t)0x00020000) |
| #define | PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) |
| #define | PWR_CSR_REGRDY PWR_CSR_VOSRDY |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
| #define | RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) |
| #define | RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) |
| #define | RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) |
| #define | RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) |
| #define | RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) |
| #define | RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
| #define | RCC_CR_HSICAL_0 ((uint32_t)0x00000100) |
| #define | RCC_CR_HSICAL_1 ((uint32_t)0x00000200) |
| #define | RCC_CR_HSICAL_2 ((uint32_t)0x00000400) |
| #define | RCC_CR_HSICAL_3 ((uint32_t)0x00000800) |
| #define | RCC_CR_HSICAL_4 ((uint32_t)0x00001000) |
| #define | RCC_CR_HSICAL_5 ((uint32_t)0x00002000) |
| #define | RCC_CR_HSICAL_6 ((uint32_t)0x00004000) |
| #define | RCC_CR_HSICAL_7 ((uint32_t)0x00008000) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_CSSON ((uint32_t)0x00080000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CR_PLLI2SON ((uint32_t)0x04000000) |
| #define | RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) |
| #define | RCC_CR_PLLSAION ((uint32_t)0x10000000) |
| #define | RCC_CR_PLLSAIRDY ((uint32_t)0x20000000) |
| #define | RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) |
| #define | RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) |
| #define | RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) |
| #define | RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) |
| #define | RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) |
| #define | RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) |
| #define | RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) |
| #define | RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) |
| #define | RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) |
| #define | RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) |
| #define | RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) |
| #define | RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) |
| #define | RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) |
| #define | RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) |
| #define | RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) |
| #define | RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) |
| #define | RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) |
| #define | RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) |
| #define | RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) |
| #define | RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) |
| #define | RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
| #define | RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) |
| #define | RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) |
| #define | RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) |
| #define | RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) |
| #define | RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) |
| #define | RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) |
| #define | RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) |
| #define | RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_MCO1 ((uint32_t)0x00600000) |
| #define | RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) |
| #define | RCC_CFGR_I2SSRC ((uint32_t)0x00800000) |
| #define | RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) |
| #define | RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) |
| #define | RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_MCO2 ((uint32_t)0xC0000000) |
| #define | RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) |
| #define | RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) |
| #define | RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) |
| #define | RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) |
| #define | RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) |
| #define | RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) |
| #define | RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) |
| #define | RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) |
| #define | RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) |
| #define | RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200) |
| #define | RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400) |
| #define | RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
| #define | RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) |
| #define | RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) |
| #define | RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000) |
| #define | RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) |
| #define | RCC_AHB1RSTR_OTGHSRST ((uint32_t)0x10000000) |
| #define | RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) |
| #define | RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) |
| #define | RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020) |
| #define | RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST |
| #define | RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) |
| #define | RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) |
| #define | RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) |
| #define | RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) |
| #define | RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000) |
| #define | RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000) |
| #define | RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) |
| #define | RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) |
| #define | RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) |
| #define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) |
| #define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) |
| #define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) |
| #define | RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000) |
| #define | RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000) |
| #define | RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000) |
| #define | RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000) |
| #define | RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
| #define | RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200) |
| #define | RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400) |
| #define | RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) |
| #define | RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) |
| #define | RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) |
| #define | RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000) |
| #define | RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) |
| #define | RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) |
| #define | RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) |
| #define | RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_APB1ENR_UART7EN ((uint32_t)0x40000000) |
| #define | RCC_APB1ENR_UART8EN ((uint32_t)0x80000000) |
| #define | RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) |
| #define | RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) |
| #define | RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) |
| #define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) |
| #define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) |
| #define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) |
| #define | RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000) |
| #define | RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000) |
| #define | RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000) |
| #define | RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) |
| #define | RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) |
| #define | RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) |
| #define | RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) |
| #define | RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) |
| #define | RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200) |
| #define | RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400) |
| #define | RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) |
| #define | RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) |
| #define | RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) |
| #define | RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) |
| #define | RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) |
| #define | RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000) |
| #define | RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) |
| #define | RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) |
| #define | RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000) |
| #define | RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) |
| #define | RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) |
| #define | RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) |
| #define | RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) |
| #define | RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) |
| #define | RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) |
| #define | RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) |
| #define | RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) |
| #define | RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) |
| #define | RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
| #define | RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
| #define | RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) |
| #define | RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) |
| #define | RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
| #define | RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
| #define | RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
| #define | RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
| #define | RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
| #define | RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
| #define | RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
| #define | RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) |
| #define | RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) |
| #define | RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) |
| #define | RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
| #define | RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
| #define | RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000) |
| #define | RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000) |
| #define | RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) |
| #define | RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) |
| #define | RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) |
| #define | RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
| #define | RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000) |
| #define | RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) |
| #define | RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) |
| #define | RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) |
| #define | RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000) |
| #define | RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000) |
| #define | RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000) |
| #define | RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000) |
| #define | RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| #define | RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| #define | RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| #define | RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| #define | RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| #define | RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| #define | RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| #define | RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_BORRSTF ((uint32_t)0x02000000) |
| #define | RCC_CSR_PADRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_WDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) |
| #define | RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) |
| #define | RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) |
| #define | RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) |
| #define | RCC_PLLSAICFGR_PLLI2SN ((uint32_t)0x00007FC0) |
| #define | RCC_PLLSAICFGR_PLLI2SQ ((uint32_t)0x0F000000) |
| #define | RCC_PLLSAICFGR_PLLI2SR ((uint32_t)0x70000000) |
| #define | RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F) |
| #define | RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00) |
| #define | RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000) |
| #define | RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000) |
| #define | RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000) |
| #define | RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000) |
| #define | RNG_CR_RNGEN ((uint32_t)0x00000004) |
| #define | RNG_CR_IE ((uint32_t)0x00000008) |
| #define | RNG_SR_DRDY ((uint32_t)0x00000001) |
| #define | RNG_SR_CECS ((uint32_t)0x00000002) |
| #define | RNG_SR_SECS ((uint32_t)0x00000004) |
| #define | RNG_SR_CEIS ((uint32_t)0x00000020) |
| #define | RNG_SR_SEIS ((uint32_t)0x00000040) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_COSEL ((uint32_t)0x00080000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_WUTIE ((uint32_t)0x00004000) |
| #define | RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_WUTE ((uint32_t)0x00000400) |
| #define | RTC_CR_ALRBE ((uint32_t)0x00000200) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_DCE ((uint32_t)0x00000080) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| #define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| #define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| #define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| #define | RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_WUTF ((uint32_t)0x00000400) |
| #define | RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_SHPF ((uint32_t)0x00000008) |
| #define | RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| #define | RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) |
| #define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| #define | RTC_CALIBR_DCS ((uint32_t)0x00000080) |
| #define | RTC_CALIBR_DC ((uint32_t)0x0000001F) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| #define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_CALR_CALP ((uint32_t)0x00008000) |
| #define | RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| #define | RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| #define | RTC_CALR_CALM ((uint32_t)0x000001FF) |
| #define | RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| #define | RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| #define | RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| #define | RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| #define | RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| #define | RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| #define | RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| #define | RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| #define | RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) |
| #define | RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) |
| #define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| #define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| #define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| #define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| #define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| #define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| #define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| #define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| #define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| #define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| #define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| #define | SAI_GCR_SYNCIN ((uint32_t)0x00000003) |
| #define | SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) |
| #define | SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) |
| #define | SAI_GCR_SYNCOUT ((uint32_t)0x00000030) |
| #define | SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) |
| #define | SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) |
| #define | SAI_xCR1_MODE ((uint32_t)0x00000003) |
| #define | SAI_xCR1_MODE_0 ((uint32_t)0x00000001) |
| #define | SAI_xCR1_MODE_1 ((uint32_t)0x00000002) |
| #define | SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) |
| #define | SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) |
| #define | SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) |
| #define | SAI_xCR1_DS ((uint32_t)0x000000E0) |
| #define | SAI_xCR1_DS_0 ((uint32_t)0x00000020) |
| #define | SAI_xCR1_DS_1 ((uint32_t)0x00000040) |
| #define | SAI_xCR1_DS_2 ((uint32_t)0x00000080) |
| #define | SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) |
| #define | SAI_xCR1_CKSTR ((uint32_t)0x00000200) |
| #define | SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) |
| #define | SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) |
| #define | SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) |
| #define | SAI_xCR1_MONO ((uint32_t)0x00001000) |
| #define | SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) |
| #define | SAI_xCR1_SAIEN ((uint32_t)0x00010000) |
| #define | SAI_xCR1_DMAEN ((uint32_t)0x00020000) |
| #define | SAI_xCR1_NODIV ((uint32_t)0x00080000) |
| #define | SAI_xCR1_MCKDIV ((uint32_t)0x00780000) |
| #define | SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) |
| #define | SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) |
| #define | SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) |
| #define | SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) |
| #define | SAI_xCR2_FTH ((uint32_t)0x00000003) |
| #define | SAI_xCR2_FTH_0 ((uint32_t)0x00000001) |
| #define | SAI_xCR2_FTH_1 ((uint32_t)0x00000002) |
| #define | SAI_xCR2_FFLUSH ((uint32_t)0x00000008) |
| #define | SAI_xCR2_TRIS ((uint32_t)0x00000010) |
| #define | SAI_xCR2_MUTE ((uint32_t)0x00000020) |
| #define | SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) |
| #define | SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) |
| #define | SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) |
| #define | SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) |
| #define | SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) |
| #define | SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) |
| #define | SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) |
| #define | SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) |
| #define | SAI_xCR2_CPL ((uint32_t)0x00080000) |
| #define | SAI_xCR2_COMP ((uint32_t)0x0000C000) |
| #define | SAI_xCR2_COMP_0 ((uint32_t)0x00004000) |
| #define | SAI_xCR2_COMP_1 ((uint32_t)0x00008000) |
| #define | SAI_xFRCR_FRL ((uint32_t)0x000000FF) |
| #define | SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) |
| #define | SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) |
| #define | SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) |
| #define | SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) |
| #define | SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) |
| #define | SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) |
| #define | SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) |
| #define | SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) |
| #define | SAI_xFRCR_FSALL ((uint32_t)0x00007F00) |
| #define | SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) |
| #define | SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) |
| #define | SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) |
| #define | SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) |
| #define | SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) |
| #define | SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) |
| #define | SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) |
| #define | SAI_xFRCR_FSDEF ((uint32_t)0x00010000) |
| #define | SAI_xFRCR_FSPO ((uint32_t)0x00020000) |
| #define | SAI_xFRCR_FSOFF ((uint32_t)0x00040000) |
| #define | SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) |
| #define | SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) |
| #define | SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) |
| #define | SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) |
| #define | SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) |
| #define | SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) |
| #define | SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) |
| #define | SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) |
| #define | SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) |
| #define | SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) |
| #define | SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) |
| #define | SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) |
| #define | SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) |
| #define | SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) |
| #define | SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) |
| #define | SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) |
| #define | SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) |
| #define | SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) |
| #define | SAI_xIMR_FREQIE ((uint32_t)0x00000008) |
| #define | SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) |
| #define | SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) |
| #define | SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) |
| #define | SAI_xSR_OVRUDR ((uint32_t)0x00000001) |
| #define | SAI_xSR_MUTEDET ((uint32_t)0x00000002) |
| #define | SAI_xSR_WCKCFG ((uint32_t)0x00000004) |
| #define | SAI_xSR_FREQ ((uint32_t)0x00000008) |
| #define | SAI_xSR_CNRDY ((uint32_t)0x00000010) |
| #define | SAI_xSR_AFSDET ((uint32_t)0x00000020) |
| #define | SAI_xSR_LFSDET ((uint32_t)0x00000040) |
| #define | SAI_xSR_FLVL ((uint32_t)0x00070000) |
| #define | SAI_xSR_FLVL_0 ((uint32_t)0x00010000) |
| #define | SAI_xSR_FLVL_1 ((uint32_t)0x00020000) |
| #define | SAI_xSR_FLVL_2 ((uint32_t)0x00030000) |
| #define | SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) |
| #define | SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) |
| #define | SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) |
| #define | SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) |
| #define | SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) |
| #define | SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) |
| #define | SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) |
| #define | SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint16_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint16_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_DFF ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint8_t)0x01) |
| #define | SPI_CR2_TXDMAEN ((uint8_t)0x02) |
| #define | SPI_CR2_SSOE ((uint8_t)0x04) |
| #define | SPI_CR2_ERRIE ((uint8_t)0x20) |
| #define | SPI_CR2_RXNEIE ((uint8_t)0x40) |
| #define | SPI_CR2_TXEIE ((uint8_t)0x80) |
| #define | SPI_SR_RXNE ((uint8_t)0x01) |
| #define | SPI_SR_TXE ((uint8_t)0x02) |
| #define | SPI_SR_CHSIDE ((uint8_t)0x04) |
| #define | SPI_SR_UDR ((uint8_t)0x08) |
| #define | SPI_SR_CRCERR ((uint8_t)0x10) |
| #define | SPI_SR_MODF ((uint8_t)0x20) |
| #define | SPI_SR_OVR ((uint8_t)0x40) |
| #define | SPI_SR_BSY ((uint8_t)0x80) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) |
| #define | SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) |
| #define | SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) |
| #define | SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) |
| #define | SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400) |
| #define | SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800) |
| #define | SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) |
| #define | SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) |
| #define | SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) |
| #define | SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) |
| #define | SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) |
| #define | SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) |
| #define | SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) |
| #define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) |
| #define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) |
| #define | SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) |
| #define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) |
| #define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) |
| #define | SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008) |
| #define | SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) |
| #define | SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) |
| #define | SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) |
| #define | SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) |
| #define | SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) |
| #define | SYSCFG_CMPCR_READY ((uint32_t)0x00000100) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCPC ((uint16_t)0x0001) |
| #define | TIM_CR2_CCUS ((uint16_t)0x0004) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_CR2_OIS1 ((uint16_t)0x0100) |
| #define | TIM_CR2_OIS1N ((uint16_t)0x0200) |
| #define | TIM_CR2_OIS2 ((uint16_t)0x0400) |
| #define | TIM_CR2_OIS2N ((uint16_t)0x0800) |
| #define | TIM_CR2_OIS3 ((uint16_t)0x1000) |
| #define | TIM_CR2_OIS3N ((uint16_t)0x2000) |
| #define | TIM_CR2_OIS4 ((uint16_t)0x4000) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_COMIE ((uint16_t)0x0020) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_BIE ((uint16_t)0x0080) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_COMDE ((uint16_t)0x2000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_COMIF ((uint16_t)0x0020) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_BIF ((uint16_t)0x0080) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_COMG ((uint8_t)0x20) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_EGR_BG ((uint8_t)0x80) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NE ((uint16_t)0x0004) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NE ((uint16_t)0x0040) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NE ((uint16_t)0x0400) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_RCR_REP ((uint8_t)0xFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_BDTR_DTG ((uint16_t)0x00FF) |
| #define | TIM_BDTR_DTG_0 ((uint16_t)0x0001) |
| #define | TIM_BDTR_DTG_1 ((uint16_t)0x0002) |
| #define | TIM_BDTR_DTG_2 ((uint16_t)0x0004) |
| #define | TIM_BDTR_DTG_3 ((uint16_t)0x0008) |
| #define | TIM_BDTR_DTG_4 ((uint16_t)0x0010) |
| #define | TIM_BDTR_DTG_5 ((uint16_t)0x0020) |
| #define | TIM_BDTR_DTG_6 ((uint16_t)0x0040) |
| #define | TIM_BDTR_DTG_7 ((uint16_t)0x0080) |
| #define | TIM_BDTR_LOCK ((uint16_t)0x0300) |
| #define | TIM_BDTR_LOCK_0 ((uint16_t)0x0100) |
| #define | TIM_BDTR_LOCK_1 ((uint16_t)0x0200) |
| #define | TIM_BDTR_OSSI ((uint16_t)0x0400) |
| #define | TIM_BDTR_OSSR ((uint16_t)0x0800) |
| #define | TIM_BDTR_BKE ((uint16_t)0x1000) |
| #define | TIM_BDTR_BKP ((uint16_t)0x2000) |
| #define | TIM_BDTR_AOE ((uint16_t)0x4000) |
| #define | TIM_BDTR_MOE ((uint16_t)0x8000) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM_OR_TI4_RMP ((uint16_t)0x00C0) |
| #define | TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) |
| #define | TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) |
| #define | TIM_OR_ITR1_RMP ((uint16_t)0x0C00) |
| #define | TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) |
| #define | TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) |
| #define | USART_SR_PE ((uint16_t)0x0001) |
| #define | USART_SR_FE ((uint16_t)0x0002) |
| #define | USART_SR_NE ((uint16_t)0x0004) |
| #define | USART_SR_ORE ((uint16_t)0x0008) |
| #define | USART_SR_IDLE ((uint16_t)0x0010) |
| #define | USART_SR_RXNE ((uint16_t)0x0020) |
| #define | USART_SR_TC ((uint16_t)0x0040) |
| #define | USART_SR_TXE ((uint16_t)0x0080) |
| #define | USART_SR_LBD ((uint16_t)0x0100) |
| #define | USART_SR_CTS ((uint16_t)0x0200) |
| #define | USART_DR_DR ((uint16_t)0x01FF) |
| #define | USART_BRR_DIV_Fraction ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) |
| #define | USART_CR1_SBK ((uint16_t)0x0001) |
| #define | USART_CR1_RWU ((uint16_t)0x0002) |
| #define | USART_CR1_RE ((uint16_t)0x0004) |
| #define | USART_CR1_TE ((uint16_t)0x0008) |
| #define | USART_CR1_IDLEIE ((uint16_t)0x0010) |
| #define | USART_CR1_RXNEIE ((uint16_t)0x0020) |
| #define | USART_CR1_TCIE ((uint16_t)0x0040) |
| #define | USART_CR1_TXEIE ((uint16_t)0x0080) |
| #define | USART_CR1_PEIE ((uint16_t)0x0100) |
| #define | USART_CR1_PS ((uint16_t)0x0200) |
| #define | USART_CR1_PCE ((uint16_t)0x0400) |
| #define | USART_CR1_WAKE ((uint16_t)0x0800) |
| #define | USART_CR1_M ((uint16_t)0x1000) |
| #define | USART_CR1_UE ((uint16_t)0x2000) |
| #define | USART_CR1_OVER8 ((uint16_t)0x8000) |
| #define | USART_CR2_ADD ((uint16_t)0x000F) |
| #define | USART_CR2_LBDL ((uint16_t)0x0020) |
| #define | USART_CR2_LBDIE ((uint16_t)0x0040) |
| #define | USART_CR2_LBCL ((uint16_t)0x0100) |
| #define | USART_CR2_CPHA ((uint16_t)0x0200) |
| #define | USART_CR2_CPOL ((uint16_t)0x0400) |
| #define | USART_CR2_CLKEN ((uint16_t)0x0800) |
| #define | USART_CR2_STOP ((uint16_t)0x3000) |
| #define | USART_CR2_STOP_0 ((uint16_t)0x1000) |
| #define | USART_CR2_STOP_1 ((uint16_t)0x2000) |
| #define | USART_CR2_LINEN ((uint16_t)0x4000) |
| #define | USART_CR3_EIE ((uint16_t)0x0001) |
| #define | USART_CR3_IREN ((uint16_t)0x0002) |
| #define | USART_CR3_IRLP ((uint16_t)0x0004) |
| #define | USART_CR3_HDSEL ((uint16_t)0x0008) |
| #define | USART_CR3_NACK ((uint16_t)0x0010) |
| #define | USART_CR3_SCEN ((uint16_t)0x0020) |
| #define | USART_CR3_DMAR ((uint16_t)0x0040) |
| #define | USART_CR3_DMAT ((uint16_t)0x0080) |
| #define | USART_CR3_RTSE ((uint16_t)0x0100) |
| #define | USART_CR3_CTSE ((uint16_t)0x0200) |
| #define | USART_CR3_CTSIE ((uint16_t)0x0400) |
| #define | USART_CR3_ONEBIT ((uint16_t)0x0800) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_PSC_0 ((uint16_t)0x0001) |
| #define | USART_GTPR_PSC_1 ((uint16_t)0x0002) |
| #define | USART_GTPR_PSC_2 ((uint16_t)0x0004) |
| #define | USART_GTPR_PSC_3 ((uint16_t)0x0008) |
| #define | USART_GTPR_PSC_4 ((uint16_t)0x0010) |
| #define | USART_GTPR_PSC_5 ((uint16_t)0x0020) |
| #define | USART_GTPR_PSC_6 ((uint16_t)0x0040) |
| #define | USART_GTPR_PSC_7 ((uint16_t)0x0080) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| #define | DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) |
| #define | DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) |
| #define | DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) |
| #define | DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
| #define | DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) |
| #define | DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) |
| #define | DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) |
| #define | ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ |
| #define | ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ |
| #define | ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ |
| #define | ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ |
| #define | ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ |
| #define | ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ |
| #define | ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ |
| #define | ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ |
| #define | ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ |
| #define | ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ |
| #define | ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ |
| #define | ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ |
| #define | ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ |
| #define | ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ |
| #define | ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ |
| #define | ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ |
| #define | ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ |
| #define | ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ |
| #define | ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ |
| #define | ETH_MACCR_BL |
| #define | ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ |
| #define | ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ |
| #define | ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ |
| #define | ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ |
| #define | ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ |
| #define | ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ |
| #define | ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ |
| #define | ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ |
| #define | ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ |
| #define | ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ |
| #define | ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ |
| #define | ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ |
| #define | ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ |
| #define | ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| #define | ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ |
| #define | ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ |
| #define | ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ |
| #define | ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ |
| #define | ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ |
| #define | ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ |
| #define | ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ |
| #define | ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ |
| #define | ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ |
| #define | ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ |
| #define | ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ |
| #define | ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ |
| #define | ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
| #define | ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
| #define | ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| #define | ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| #define | ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
| #define | ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ |
| #define | ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ |
| #define | ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ |
| #define | ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ |
| #define | ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ |
| #define | ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ |
| #define | ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ |
| #define | ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ |
| #define | ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ |
| #define | ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ |
| #define | ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ |
| #define | ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ |
| #define | ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ |
| #define | ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ |
| #define | ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ |
| #define | ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ |
| #define | ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ |
| #define | ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ |
| #define | ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ |
| #define | ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ |
| #define | ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ |
| #define | ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ |
| #define | ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ |
| #define | ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ |
| #define | ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ |
| #define | ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ |
| #define | ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ |
| #define | ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ |
| #define | ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ |
| #define | ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ |
| #define | ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ |
| #define | ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ |
| #define | ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ |
| #define | ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| #define | ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ |
| #define | ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ |
| #define | ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ |
| #define | ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ |
| #define | ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ |
| #define | ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ |
| #define | ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ |
| #define | ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ |
| #define | ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ |
| #define | ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ |
| #define | ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ |
| #define | ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ |
| #define | ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ |
| #define | ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ |
| #define | ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ |
| #define | ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ |
| #define | ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ |
| #define | ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ |
| #define | ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ |
| #define | ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ |
| #define | ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ |
| #define | ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ |
| #define | ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ |
| #define | ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ |
| #define | ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ |
| #define | ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ |
| #define | ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ |
| #define | ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ |
| #define | ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ |
| #define | ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ |
| #define | ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ |
| #define | ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ |
| #define | ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ |
| #define | ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ |
| #define | ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ |
| #define | ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ |
| #define | ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ |
| #define | ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ |
| #define | ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ |
| #define | ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ |
| #define | ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ |
| #define | ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ |
| #define | ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ |
| #define | ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ |
| #define | ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ |
| #define | ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ |
| #define | ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ |
| #define | ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ |
| #define | ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ |
| #define | ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ |
| #define | ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| #define | ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| #define | ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| #define | ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| #define | ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ |
| #define | ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ |
| #define | ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| #define | ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| #define | ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| #define | ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| #define | ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ |
| #define | ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ |
| #define | ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ |
| #define | ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ |
| #define | ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ |
| #define | ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ |
| #define | ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ |
| #define | ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ |
| #define | ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ |
| #define | ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ |
| #define | ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ |
| #define | ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ |
| #define | ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ |
| #define | ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ |
| #define | ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| #define | ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ |
| #define | ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ |
| #define | ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ |
| #define | ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ |
| #define | ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ |
| #define | ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ |
| #define | ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ |
| #define | ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ |
| #define | ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ |
| #define | ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ |
| #define | ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ |
| #define | ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ |
| #define | ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ |
| #define | ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ |
| #define | ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ |
| #define | ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ |
| #define | ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ |
| #define | ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ |
| #define | ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ |
| #define | ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ |
| #define | ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ |
| #define | ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ |
| #define | ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ |
| #define | ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ |
| #define | ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ |
| #define | ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ |
| #define | ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ |
| #define | ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ |
| #define | ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ |
| #define | ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ |
| #define | ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ |
| #define | ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ |
| #define | ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ |
| #define | ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ |
| #define | ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ |
| #define | ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| #define | ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| #define | ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| #define | ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| #define | ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| #define | ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ |
| #define | ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ |
| #define | ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ |
| #define | ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ |
| #define | ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| #define | ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ |
| #define | ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ |
| #define | ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ |
| #define | ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ |
| #define | ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ |
| #define | ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ |
| #define | ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ |
| #define | ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ |
| #define | ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ |
| #define | ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ |
| #define | ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ |
| #define | ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ |
| #define | ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ |
| #define | ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ |
| #define | ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ |
| #define | ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ |
| #define | ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ |
| #define | ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ |
| #define | ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ |
| #define | ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ |
| #define | ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ |
| #define | ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ |
| #define | ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ |
| #define | ADC_SR_AWD ((uint32_t)0x00000001) |
| #define | ADC_SR_EOC ((uint32_t)0x00000002) |
| #define | ADC_SR_JEOC ((uint32_t)0x00000004) |
| #define | ADC_SR_JSTRT ((uint32_t)0x00000008) |
| #define | ADC_SR_STRT ((uint32_t)0x00000010) |
| #define | ADC_SR_OVR ((uint32_t)0x00000020) |
| #define | ADC_SR_ADONS ((uint32_t)0x00000040) |
| #define | ADC_SR_RCNR ((uint32_t)0x00000100) |
| #define | ADC_SR_JCNR ((uint32_t)0x00000200) |
| #define | ADC_CR1_AWDCH ((uint32_t)0x0000001F) |
| #define | ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) |
| #define | ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) |
| #define | ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) |
| #define | ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) |
| #define | ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) |
| #define | ADC_CR1_EOCIE ((uint32_t)0x00000020) |
| #define | ADC_CR1_AWDIE ((uint32_t)0x00000040) |
| #define | ADC_CR1_JEOCIE ((uint32_t)0x00000080) |
| #define | ADC_CR1_SCAN ((uint32_t)0x00000100) |
| #define | ADC_CR1_AWDSGL ((uint32_t)0x00000200) |
| #define | ADC_CR1_JAUTO ((uint32_t)0x00000400) |
| #define | ADC_CR1_DISCEN ((uint32_t)0x00000800) |
| #define | ADC_CR1_JDISCEN ((uint32_t)0x00001000) |
| #define | ADC_CR1_DISCNUM ((uint32_t)0x0000E000) |
| #define | ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) |
| #define | ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) |
| #define | ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) |
| #define | ADC_CR1_PDD ((uint32_t)0x00010000) |
| #define | ADC_CR1_PDI ((uint32_t)0x00020000) |
| #define | ADC_CR1_JAWDEN ((uint32_t)0x00400000) |
| #define | ADC_CR1_AWDEN ((uint32_t)0x00800000) |
| #define | ADC_CR1_RES ((uint32_t)0x03000000) |
| #define | ADC_CR1_RES_0 ((uint32_t)0x01000000) |
| #define | ADC_CR1_RES_1 ((uint32_t)0x02000000) |
| #define | ADC_CR1_OVRIE ((uint32_t)0x04000000) |
| #define | ADC_CR2_ADON ((uint32_t)0x00000001) |
| #define | ADC_CR2_CONT ((uint32_t)0x00000002) |
| #define | ADC_CR2_CFG ((uint32_t)0x00000004) |
| #define | ADC_CR2_DELS ((uint32_t)0x00000070) |
| #define | ADC_CR2_DELS_0 ((uint32_t)0x00000010) |
| #define | ADC_CR2_DELS_1 ((uint32_t)0x00000020) |
| #define | ADC_CR2_DELS_2 ((uint32_t)0x00000040) |
| #define | ADC_CR2_DMA ((uint32_t)0x00000100) |
| #define | ADC_CR2_DDS ((uint32_t)0x00000200) |
| #define | ADC_CR2_EOCS ((uint32_t)0x00000400) |
| #define | ADC_CR2_ALIGN ((uint32_t)0x00000800) |
| #define | ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) |
| #define | ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) |
| #define | ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) |
| #define | ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) |
| #define | ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) |
| #define | ADC_CR2_JEXTEN ((uint32_t)0x00300000) |
| #define | ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) |
| #define | ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) |
| #define | ADC_CR2_JSWSTART ((uint32_t)0x00400000) |
| #define | ADC_CR2_EXTSEL ((uint32_t)0x0F000000) |
| #define | ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) |
| #define | ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) |
| #define | ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) |
| #define | ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) |
| #define | ADC_CR2_EXTEN ((uint32_t)0x30000000) |
| #define | ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) |
| #define | ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) |
| #define | ADC_CR2_SWSTART ((uint32_t)0x40000000) |
| #define | ADC_SMPR1_SMP20 ((uint32_t)0x00000007) |
| #define | ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR1_SMP21 ((uint32_t)0x00000038) |
| #define | ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR1_SMP24 ((uint32_t)0x00007000) |
| #define | ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR1_SMP25 ((uint32_t)0x00038000) |
| #define | ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR1_SMP28 ((uint32_t)0x07000000) |
| #define | ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR1_SMP29 ((uint32_t)0x38000000) |
| #define | ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) |
| #define | ADC_SMPR2_SMP10 ((uint32_t)0x00000007) |
| #define | ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR2_SMP11 ((uint32_t)0x00000038) |
| #define | ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR2_SMP14 ((uint32_t)0x00007000) |
| #define | ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR2_SMP15 ((uint32_t)0x00038000) |
| #define | ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR2_SMP18 ((uint32_t)0x07000000) |
| #define | ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR2_SMP19 ((uint32_t)0x38000000) |
| #define | ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) |
| #define | ADC_SMPR3_SMP0 ((uint32_t)0x00000007) |
| #define | ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR3_SMP1 ((uint32_t)0x00000038) |
| #define | ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) |
| #define | ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) |
| #define | ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) |
| #define | ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) |
| #define | ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) |
| #define | ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) |
| #define | ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) |
| #define | ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) |
| #define | ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) |
| #define | ADC_SMPR3_SMP4 ((uint32_t)0x00007000) |
| #define | ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) |
| #define | ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) |
| #define | ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) |
| #define | ADC_SMPR3_SMP5 ((uint32_t)0x00038000) |
| #define | ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) |
| #define | ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) |
| #define | ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) |
| #define | ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) |
| #define | ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) |
| #define | ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) |
| #define | ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) |
| #define | ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) |
| #define | ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) |
| #define | ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) |
| #define | ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) |
| #define | ADC_SMPR3_SMP8 ((uint32_t)0x07000000) |
| #define | ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) |
| #define | ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) |
| #define | ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) |
| #define | ADC_SMPR3_SMP9 ((uint32_t)0x38000000) |
| #define | ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) |
| #define | ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) |
| #define | ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) |
| #define | ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) |
| #define | ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) |
| #define | ADC_HTR_HT ((uint32_t)0x00000FFF) |
| #define | ADC_LTR_LT ((uint32_t)0x00000FFF) |
| #define | ADC_SQR1_L ((uint32_t)0x00F00000) |
| #define | ADC_SQR1_L_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR1_L_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR1_L_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR1_L_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR1_SQ28 ((uint32_t)0x000F8000) |
| #define | ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR1_SQ27 ((uint32_t)0x00007C00) |
| #define | ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR1_SQ26 ((uint32_t)0x000003E0) |
| #define | ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR1_SQ25 ((uint32_t)0x0000001F) |
| #define | ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ19 ((uint32_t)0x0000001F) |
| #define | ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR2_SQ20 ((uint32_t)0x000003E0) |
| #define | ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR2_SQ21 ((uint32_t)0x00007C00) |
| #define | ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR2_SQ22 ((uint32_t)0x000F8000) |
| #define | ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR2_SQ23 ((uint32_t)0x01F00000) |
| #define | ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR2_SQ24 ((uint32_t)0x3E000000) |
| #define | ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR3_SQ13 ((uint32_t)0x0000001F) |
| #define | ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR3_SQ14 ((uint32_t)0x000003E0) |
| #define | ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR3_SQ15 ((uint32_t)0x00007C00) |
| #define | ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR3_SQ16 ((uint32_t)0x000F8000) |
| #define | ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR3_SQ17 ((uint32_t)0x01F00000) |
| #define | ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR3_SQ18 ((uint32_t)0x3E000000) |
| #define | ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR4_SQ7 ((uint32_t)0x0000001F) |
| #define | ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR4_SQ8 ((uint32_t)0x000003E0) |
| #define | ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR4_SQ9 ((uint32_t)0x00007C00) |
| #define | ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR4_SQ10 ((uint32_t)0x000F8000) |
| #define | ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR4_SQ11 ((uint32_t)0x01F00000) |
| #define | ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR4_SQ12 ((uint32_t)0x3E000000) |
| #define | ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) |
| #define | ADC_SQR5_SQ1 ((uint32_t)0x0000001F) |
| #define | ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_SQR5_SQ2 ((uint32_t)0x000003E0) |
| #define | ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_SQR5_SQ3 ((uint32_t)0x00007C00) |
| #define | ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_SQR5_SQ4 ((uint32_t)0x000F8000) |
| #define | ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_SQR5_SQ5 ((uint32_t)0x01F00000) |
| #define | ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) |
| #define | ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) |
| #define | ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) |
| #define | ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) |
| #define | ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) |
| #define | ADC_SQR5_SQ6 ((uint32_t)0x3E000000) |
| #define | ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) |
| #define | ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) |
| #define | ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) |
| #define | ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) |
| #define | ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) |
| #define | ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) |
| #define | ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) |
| #define | ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) |
| #define | ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) |
| #define | ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) |
| #define | ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) |
| #define | ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) |
| #define | ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) |
| #define | ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) |
| #define | ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) |
| #define | ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) |
| #define | ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) |
| #define | ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) |
| #define | ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) |
| #define | ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) |
| #define | ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) |
| #define | ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) |
| #define | ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) |
| #define | ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) |
| #define | ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) |
| #define | ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) |
| #define | ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) |
| #define | ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) |
| #define | ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) |
| #define | ADC_JSQR_JL ((uint32_t)0x00300000) |
| #define | ADC_JSQR_JL_0 ((uint32_t)0x00100000) |
| #define | ADC_JSQR_JL_1 ((uint32_t)0x00200000) |
| #define | ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) |
| #define | ADC_DR_DATA ((uint32_t)0x0000FFFF) |
| #define | ADC_SMPR3_SMP30 ((uint32_t)0x00000007) |
| #define | ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) |
| #define | ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) |
| #define | ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) |
| #define | ADC_SMPR3_SMP31 ((uint32_t)0x00000038) |
| #define | ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) |
| #define | ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) |
| #define | ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) |
| #define | ADC_CSR_AWD1 ((uint32_t)0x00000001) |
| #define | ADC_CSR_EOC1 ((uint32_t)0x00000002) |
| #define | ADC_CSR_JEOC1 ((uint32_t)0x00000004) |
| #define | ADC_CSR_JSTRT1 ((uint32_t)0x00000008) |
| #define | ADC_CSR_STRT1 ((uint32_t)0x00000010) |
| #define | ADC_CSR_OVR1 ((uint32_t)0x00000020) |
| #define | ADC_CSR_ADONS1 ((uint32_t)0x00000040) |
| #define | ADC_CCR_ADCPRE ((uint32_t)0x00030000) |
| #define | ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) |
| #define | ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) |
| #define | ADC_CCR_TSVREFE ((uint32_t)0x00800000) |
| #define | AES_CR_EN ((uint32_t)0x00000001) |
| #define | AES_CR_DATATYPE ((uint32_t)0x00000006) |
| #define | AES_CR_DATATYPE_0 ((uint32_t)0x00000002) |
| #define | AES_CR_DATATYPE_1 ((uint32_t)0x00000004) |
| #define | AES_CR_MODE ((uint32_t)0x00000018) |
| #define | AES_CR_MODE_0 ((uint32_t)0x00000008) |
| #define | AES_CR_MODE_1 ((uint32_t)0x00000010) |
| #define | AES_CR_CHMOD ((uint32_t)0x00000060) |
| #define | AES_CR_CHMOD_0 ((uint32_t)0x00000020) |
| #define | AES_CR_CHMOD_1 ((uint32_t)0x00000040) |
| #define | AES_CR_CCFC ((uint32_t)0x00000080) |
| #define | AES_CR_ERRC ((uint32_t)0x00000100) |
| #define | AES_CR_CCIE ((uint32_t)0x00000200) |
| #define | AES_CR_ERRIE ((uint32_t)0x00000400) |
| #define | AES_CR_DMAINEN ((uint32_t)0x00000800) |
| #define | AES_CR_DMAOUTEN ((uint32_t)0x00001000) |
| #define | AES_SR_CCF ((uint32_t)0x00000001) |
| #define | AES_SR_RDERR ((uint32_t)0x00000002) |
| #define | AES_SR_WRERR ((uint32_t)0x00000004) |
| #define | AES_DINR ((uint32_t)0x0000FFFF) |
| #define | AES_DOUTR ((uint32_t)0x0000FFFF) |
| #define | AES_KEYR0 ((uint32_t)0x0000FFFF) |
| #define | AES_KEYR1 ((uint32_t)0x0000FFFF) |
| #define | AES_KEYR2 ((uint32_t)0x0000FFFF) |
| #define | AES_KEYR3 ((uint32_t)0x0000FFFF) |
| #define | AES_IVR0 ((uint32_t)0x0000FFFF) |
| #define | AES_IVR1 ((uint32_t)0x0000FFFF) |
| #define | AES_IVR2 ((uint32_t)0x0000FFFF) |
| #define | AES_IVR3 ((uint32_t)0x0000FFFF) |
| #define | COMP_CSR_10KPU ((uint32_t)0x00000001) |
| #define | COMP_CSR_400KPU ((uint32_t)0x00000002) |
| #define | COMP_CSR_10KPD ((uint32_t)0x00000004) |
| #define | COMP_CSR_400KPD ((uint32_t)0x00000008) |
| #define | COMP_CSR_CMP1EN ((uint32_t)0x00000010) |
| #define | COMP_CSR_SW1 ((uint32_t)0x00000020) |
| #define | COMP_CSR_CMP1OUT ((uint32_t)0x00000080) |
| #define | COMP_CSR_SPEED ((uint32_t)0x00001000) |
| #define | COMP_CSR_CMP2OUT ((uint32_t)0x00002000) |
| #define | COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) |
| #define | COMP_CSR_WNDWE ((uint32_t)0x00020000) |
| #define | COMP_CSR_INSEL ((uint32_t)0x001C0000) |
| #define | COMP_CSR_INSEL_0 ((uint32_t)0x00040000) |
| #define | COMP_CSR_INSEL_1 ((uint32_t)0x00080000) |
| #define | COMP_CSR_INSEL_2 ((uint32_t)0x00100000) |
| #define | COMP_CSR_OUTSEL ((uint32_t)0x00E00000) |
| #define | COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) |
| #define | COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) |
| #define | COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) |
| #define | COMP_CSR_FCH3 ((uint32_t)0x04000000) |
| #define | COMP_CSR_FCH8 ((uint32_t)0x08000000) |
| #define | COMP_CSR_RCH13 ((uint32_t)0x10000000) |
| #define | COMP_CSR_CAIE ((uint32_t)0x20000000) |
| #define | COMP_CSR_CAIF ((uint32_t)0x40000000) |
| #define | COMP_CSR_TSUSP ((uint32_t)0x80000000) |
| #define | OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) |
| #define | OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) |
| #define | OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) |
| #define | OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) |
| #define | OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) |
| #define | OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) |
| #define | OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) |
| #define | OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) |
| #define | OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) |
| #define | OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) |
| #define | OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) |
| #define | OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) |
| #define | OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) |
| #define | OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) |
| #define | OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) |
| #define | OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) |
| #define | OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) |
| #define | OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) |
| #define | OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) |
| #define | OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) |
| #define | OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) |
| #define | OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) |
| #define | OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) |
| #define | OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) |
| #define | OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) |
| #define | OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) |
| #define | OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) |
| #define | OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) |
| #define | OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) |
| #define | OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) |
| #define | OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) |
| #define | OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) |
| #define | OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) |
| #define | OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) |
| #define | OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) |
| #define | OPAMP_OTR_OT_USER ((uint32_t)0x80000000) |
| #define | OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) |
| #define | OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) |
| #define | OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) |
| #define | CRC_DR_DR ((uint32_t)0xFFFFFFFF) |
| #define | CRC_IDR_IDR ((uint8_t)0xFF) |
| #define | CRC_CR_RESET ((uint32_t)0x00000001) |
| #define | DAC_CR_EN1 ((uint32_t)0x00000001) |
| #define | DAC_CR_BOFF1 ((uint32_t)0x00000002) |
| #define | DAC_CR_TEN1 ((uint32_t)0x00000004) |
| #define | DAC_CR_TSEL1 ((uint32_t)0x00000038) |
| #define | DAC_CR_TSEL1_0 ((uint32_t)0x00000008) |
| #define | DAC_CR_TSEL1_1 ((uint32_t)0x00000010) |
| #define | DAC_CR_TSEL1_2 ((uint32_t)0x00000020) |
| #define | DAC_CR_WAVE1 ((uint32_t)0x000000C0) |
| #define | DAC_CR_WAVE1_0 ((uint32_t)0x00000040) |
| #define | DAC_CR_WAVE1_1 ((uint32_t)0x00000080) |
| #define | DAC_CR_MAMP1 ((uint32_t)0x00000F00) |
| #define | DAC_CR_MAMP1_0 ((uint32_t)0x00000100) |
| #define | DAC_CR_MAMP1_1 ((uint32_t)0x00000200) |
| #define | DAC_CR_MAMP1_2 ((uint32_t)0x00000400) |
| #define | DAC_CR_MAMP1_3 ((uint32_t)0x00000800) |
| #define | DAC_CR_DMAEN1 ((uint32_t)0x00001000) |
| #define | DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) |
| #define | DAC_CR_EN2 ((uint32_t)0x00010000) |
| #define | DAC_CR_BOFF2 ((uint32_t)0x00020000) |
| #define | DAC_CR_TEN2 ((uint32_t)0x00040000) |
| #define | DAC_CR_TSEL2 ((uint32_t)0x00380000) |
| #define | DAC_CR_TSEL2_0 ((uint32_t)0x00080000) |
| #define | DAC_CR_TSEL2_1 ((uint32_t)0x00100000) |
| #define | DAC_CR_TSEL2_2 ((uint32_t)0x00200000) |
| #define | DAC_CR_WAVE2 ((uint32_t)0x00C00000) |
| #define | DAC_CR_WAVE2_0 ((uint32_t)0x00400000) |
| #define | DAC_CR_WAVE2_1 ((uint32_t)0x00800000) |
| #define | DAC_CR_MAMP2 ((uint32_t)0x0F000000) |
| #define | DAC_CR_MAMP2_0 ((uint32_t)0x01000000) |
| #define | DAC_CR_MAMP2_1 ((uint32_t)0x02000000) |
| #define | DAC_CR_MAMP2_2 ((uint32_t)0x04000000) |
| #define | DAC_CR_MAMP2_3 ((uint32_t)0x08000000) |
| #define | DAC_CR_DMAEN2 ((uint32_t)0x10000000) |
| #define | DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) |
| #define | DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) |
| #define | DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) |
| #define | DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) |
| #define | DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) |
| #define | DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) |
| #define | DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) |
| #define | DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) |
| #define | DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) |
| #define | DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) |
| #define | DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) |
| #define | DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) |
| #define | DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) |
| #define | DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) |
| #define | DAC_SR_DMAUDR1 ((uint32_t)0x00002000) |
| #define | DAC_SR_DMAUDR2 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
| #define | DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| #define | DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) |
| #define | DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) |
| #define | DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) |
| #define | DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) |
| #define | DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) |
| #define | DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) |
| #define | DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) |
| #define | DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) |
| #define | DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) |
| #define | DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) |
| #define | DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) |
| #define | DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) |
| #define | DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) |
| #define | DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) |
| #define | DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) |
| #define | DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) |
| #define | DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| #define | DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| #define | DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| #define | DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| #define | DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) |
| #define | DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) |
| #define | DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) |
| #define | DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) |
| #define | DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) |
| #define | DMA_ISR_GIF1 ((uint32_t)0x00000001) |
| #define | DMA_ISR_TCIF1 ((uint32_t)0x00000002) |
| #define | DMA_ISR_HTIF1 ((uint32_t)0x00000004) |
| #define | DMA_ISR_TEIF1 ((uint32_t)0x00000008) |
| #define | DMA_ISR_GIF2 ((uint32_t)0x00000010) |
| #define | DMA_ISR_TCIF2 ((uint32_t)0x00000020) |
| #define | DMA_ISR_HTIF2 ((uint32_t)0x00000040) |
| #define | DMA_ISR_TEIF2 ((uint32_t)0x00000080) |
| #define | DMA_ISR_GIF3 ((uint32_t)0x00000100) |
| #define | DMA_ISR_TCIF3 ((uint32_t)0x00000200) |
| #define | DMA_ISR_HTIF3 ((uint32_t)0x00000400) |
| #define | DMA_ISR_TEIF3 ((uint32_t)0x00000800) |
| #define | DMA_ISR_GIF4 ((uint32_t)0x00001000) |
| #define | DMA_ISR_TCIF4 ((uint32_t)0x00002000) |
| #define | DMA_ISR_HTIF4 ((uint32_t)0x00004000) |
| #define | DMA_ISR_TEIF4 ((uint32_t)0x00008000) |
| #define | DMA_ISR_GIF5 ((uint32_t)0x00010000) |
| #define | DMA_ISR_TCIF5 ((uint32_t)0x00020000) |
| #define | DMA_ISR_HTIF5 ((uint32_t)0x00040000) |
| #define | DMA_ISR_TEIF5 ((uint32_t)0x00080000) |
| #define | DMA_ISR_GIF6 ((uint32_t)0x00100000) |
| #define | DMA_ISR_TCIF6 ((uint32_t)0x00200000) |
| #define | DMA_ISR_HTIF6 ((uint32_t)0x00400000) |
| #define | DMA_ISR_TEIF6 ((uint32_t)0x00800000) |
| #define | DMA_ISR_GIF7 ((uint32_t)0x01000000) |
| #define | DMA_ISR_TCIF7 ((uint32_t)0x02000000) |
| #define | DMA_ISR_HTIF7 ((uint32_t)0x04000000) |
| #define | DMA_ISR_TEIF7 ((uint32_t)0x08000000) |
| #define | DMA_IFCR_CGIF1 ((uint32_t)0x00000001) |
| #define | DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) |
| #define | DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) |
| #define | DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) |
| #define | DMA_IFCR_CGIF2 ((uint32_t)0x00000010) |
| #define | DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) |
| #define | DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) |
| #define | DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) |
| #define | DMA_IFCR_CGIF3 ((uint32_t)0x00000100) |
| #define | DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) |
| #define | DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) |
| #define | DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) |
| #define | DMA_IFCR_CGIF4 ((uint32_t)0x00001000) |
| #define | DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) |
| #define | DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) |
| #define | DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) |
| #define | DMA_IFCR_CGIF5 ((uint32_t)0x00010000) |
| #define | DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) |
| #define | DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) |
| #define | DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) |
| #define | DMA_IFCR_CGIF6 ((uint32_t)0x00100000) |
| #define | DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) |
| #define | DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) |
| #define | DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) |
| #define | DMA_IFCR_CGIF7 ((uint32_t)0x01000000) |
| #define | DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) |
| #define | DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) |
| #define | DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) |
| #define | DMA_CCR1_EN ((uint16_t)0x0001) |
| #define | DMA_CCR1_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR1_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR1_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR1_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR1_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR1_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR1_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR1_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR1_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR1_PL ((uint16_t)0x3000) |
| #define | DMA_CCR1_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR1_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR1_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR2_EN ((uint16_t)0x0001) |
| #define | DMA_CCR2_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR2_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR2_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR2_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR2_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR2_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR2_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR2_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR2_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR2_PL ((uint16_t)0x3000) |
| #define | DMA_CCR2_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR2_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR2_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR3_EN ((uint16_t)0x0001) |
| #define | DMA_CCR3_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR3_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR3_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR3_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR3_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR3_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR3_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR3_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR3_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR3_PL ((uint16_t)0x3000) |
| #define | DMA_CCR3_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR3_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR3_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR4_EN ((uint16_t)0x0001) |
| #define | DMA_CCR4_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR4_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR4_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR4_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR4_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR4_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR4_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR4_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR4_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR4_PL ((uint16_t)0x3000) |
| #define | DMA_CCR4_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR4_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR4_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR5_EN ((uint16_t)0x0001) |
| #define | DMA_CCR5_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR5_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR5_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR5_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR5_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR5_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR5_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR5_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR5_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR5_PL ((uint16_t)0x3000) |
| #define | DMA_CCR5_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR5_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR5_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR6_EN ((uint16_t)0x0001) |
| #define | DMA_CCR6_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR6_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR6_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR6_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR6_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR6_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR6_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR6_PSIZE ((uint16_t)0x0300) |
| #define | DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR6_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR6_PL ((uint16_t)0x3000) |
| #define | DMA_CCR6_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR6_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR6_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CCR7_EN ((uint16_t)0x0001) |
| #define | DMA_CCR7_TCIE ((uint16_t)0x0002) |
| #define | DMA_CCR7_HTIE ((uint16_t)0x0004) |
| #define | DMA_CCR7_TEIE ((uint16_t)0x0008) |
| #define | DMA_CCR7_DIR ((uint16_t)0x0010) |
| #define | DMA_CCR7_CIRC ((uint16_t)0x0020) |
| #define | DMA_CCR7_PINC ((uint16_t)0x0040) |
| #define | DMA_CCR7_MINC ((uint16_t)0x0080) |
| #define | DMA_CCR7_PSIZE , ((uint16_t)0x0300) |
| #define | DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) |
| #define | DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) |
| #define | DMA_CCR7_MSIZE ((uint16_t)0x0C00) |
| #define | DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) |
| #define | DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) |
| #define | DMA_CCR7_PL ((uint16_t)0x3000) |
| #define | DMA_CCR7_PL_0 ((uint16_t)0x1000) |
| #define | DMA_CCR7_PL_1 ((uint16_t)0x2000) |
| #define | DMA_CCR7_MEM2MEM ((uint16_t)0x4000) |
| #define | DMA_CNDTR1_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR2_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR3_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR4_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR5_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR6_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CNDTR7_NDT ((uint16_t)0xFFFF) |
| #define | DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) |
| #define | DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) |
| #define | EXTI_IMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_IMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_IMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_IMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_IMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_IMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_IMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_IMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_IMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_IMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_IMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_IMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_IMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_IMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_IMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_IMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_IMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_IMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_IMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_IMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_IMR_MR20 ((uint32_t)0x00100000) |
| #define | EXTI_IMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_IMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_IMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_EMR_MR0 ((uint32_t)0x00000001) |
| #define | EXTI_EMR_MR1 ((uint32_t)0x00000002) |
| #define | EXTI_EMR_MR2 ((uint32_t)0x00000004) |
| #define | EXTI_EMR_MR3 ((uint32_t)0x00000008) |
| #define | EXTI_EMR_MR4 ((uint32_t)0x00000010) |
| #define | EXTI_EMR_MR5 ((uint32_t)0x00000020) |
| #define | EXTI_EMR_MR6 ((uint32_t)0x00000040) |
| #define | EXTI_EMR_MR7 ((uint32_t)0x00000080) |
| #define | EXTI_EMR_MR8 ((uint32_t)0x00000100) |
| #define | EXTI_EMR_MR9 ((uint32_t)0x00000200) |
| #define | EXTI_EMR_MR10 ((uint32_t)0x00000400) |
| #define | EXTI_EMR_MR11 ((uint32_t)0x00000800) |
| #define | EXTI_EMR_MR12 ((uint32_t)0x00001000) |
| #define | EXTI_EMR_MR13 ((uint32_t)0x00002000) |
| #define | EXTI_EMR_MR14 ((uint32_t)0x00004000) |
| #define | EXTI_EMR_MR15 ((uint32_t)0x00008000) |
| #define | EXTI_EMR_MR16 ((uint32_t)0x00010000) |
| #define | EXTI_EMR_MR17 ((uint32_t)0x00020000) |
| #define | EXTI_EMR_MR18 ((uint32_t)0x00040000) |
| #define | EXTI_EMR_MR19 ((uint32_t)0x00080000) |
| #define | EXTI_EMR_MR20 ((uint32_t)0x00100000) |
| #define | EXTI_EMR_MR21 ((uint32_t)0x00200000) |
| #define | EXTI_EMR_MR22 ((uint32_t)0x00400000) |
| #define | EXTI_EMR_MR23 ((uint32_t)0x00800000) |
| #define | EXTI_RTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_RTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_RTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_RTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_RTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_RTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_RTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_RTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_RTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_RTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_RTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_RTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_RTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_RTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_RTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_RTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_RTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_RTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_RTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_RTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_RTSR_TR20 ((uint32_t)0x00100000) |
| #define | EXTI_RTSR_TR21 ((uint32_t)0x00200000) |
| #define | EXTI_RTSR_TR22 ((uint32_t)0x00400000) |
| #define | EXTI_RTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_FTSR_TR0 ((uint32_t)0x00000001) |
| #define | EXTI_FTSR_TR1 ((uint32_t)0x00000002) |
| #define | EXTI_FTSR_TR2 ((uint32_t)0x00000004) |
| #define | EXTI_FTSR_TR3 ((uint32_t)0x00000008) |
| #define | EXTI_FTSR_TR4 ((uint32_t)0x00000010) |
| #define | EXTI_FTSR_TR5 ((uint32_t)0x00000020) |
| #define | EXTI_FTSR_TR6 ((uint32_t)0x00000040) |
| #define | EXTI_FTSR_TR7 ((uint32_t)0x00000080) |
| #define | EXTI_FTSR_TR8 ((uint32_t)0x00000100) |
| #define | EXTI_FTSR_TR9 ((uint32_t)0x00000200) |
| #define | EXTI_FTSR_TR10 ((uint32_t)0x00000400) |
| #define | EXTI_FTSR_TR11 ((uint32_t)0x00000800) |
| #define | EXTI_FTSR_TR12 ((uint32_t)0x00001000) |
| #define | EXTI_FTSR_TR13 ((uint32_t)0x00002000) |
| #define | EXTI_FTSR_TR14 ((uint32_t)0x00004000) |
| #define | EXTI_FTSR_TR15 ((uint32_t)0x00008000) |
| #define | EXTI_FTSR_TR16 ((uint32_t)0x00010000) |
| #define | EXTI_FTSR_TR17 ((uint32_t)0x00020000) |
| #define | EXTI_FTSR_TR18 ((uint32_t)0x00040000) |
| #define | EXTI_FTSR_TR19 ((uint32_t)0x00080000) |
| #define | EXTI_FTSR_TR20 ((uint32_t)0x00100000) |
| #define | EXTI_FTSR_TR21 ((uint32_t)0x00200000) |
| #define | EXTI_FTSR_TR22 ((uint32_t)0x00400000) |
| #define | EXTI_FTSR_TR23 ((uint32_t)0x00800000) |
| #define | EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) |
| #define | EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) |
| #define | EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) |
| #define | EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) |
| #define | EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) |
| #define | EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) |
| #define | EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) |
| #define | EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) |
| #define | EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) |
| #define | EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) |
| #define | EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) |
| #define | EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) |
| #define | EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) |
| #define | EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) |
| #define | EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) |
| #define | EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) |
| #define | EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) |
| #define | EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) |
| #define | EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) |
| #define | EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) |
| #define | EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) |
| #define | EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) |
| #define | EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) |
| #define | EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) |
| #define | EXTI_PR_PR0 ((uint32_t)0x00000001) |
| #define | EXTI_PR_PR1 ((uint32_t)0x00000002) |
| #define | EXTI_PR_PR2 ((uint32_t)0x00000004) |
| #define | EXTI_PR_PR3 ((uint32_t)0x00000008) |
| #define | EXTI_PR_PR4 ((uint32_t)0x00000010) |
| #define | EXTI_PR_PR5 ((uint32_t)0x00000020) |
| #define | EXTI_PR_PR6 ((uint32_t)0x00000040) |
| #define | EXTI_PR_PR7 ((uint32_t)0x00000080) |
| #define | EXTI_PR_PR8 ((uint32_t)0x00000100) |
| #define | EXTI_PR_PR9 ((uint32_t)0x00000200) |
| #define | EXTI_PR_PR10 ((uint32_t)0x00000400) |
| #define | EXTI_PR_PR11 ((uint32_t)0x00000800) |
| #define | EXTI_PR_PR12 ((uint32_t)0x00001000) |
| #define | EXTI_PR_PR13 ((uint32_t)0x00002000) |
| #define | EXTI_PR_PR14 ((uint32_t)0x00004000) |
| #define | EXTI_PR_PR15 ((uint32_t)0x00008000) |
| #define | EXTI_PR_PR16 ((uint32_t)0x00010000) |
| #define | EXTI_PR_PR17 ((uint32_t)0x00020000) |
| #define | EXTI_PR_PR18 ((uint32_t)0x00040000) |
| #define | EXTI_PR_PR19 ((uint32_t)0x00080000) |
| #define | EXTI_PR_PR20 ((uint32_t)0x00100000) |
| #define | EXTI_PR_PR21 ((uint32_t)0x00200000) |
| #define | EXTI_PR_PR22 ((uint32_t)0x00400000) |
| #define | EXTI_PR_PR23 ((uint32_t)0x00800000) |
| #define | FLASH_ACR_LATENCY ((uint32_t)0x00000001) |
| #define | FLASH_ACR_PRFTEN ((uint32_t)0x00000002) |
| #define | FLASH_ACR_ACC64 ((uint32_t)0x00000004) |
| #define | FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) |
| #define | FLASH_ACR_RUN_PD ((uint32_t)0x00000010) |
| #define | FLASH_PECR_PELOCK ((uint32_t)0x00000001) |
| #define | FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) |
| #define | FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) |
| #define | FLASH_PECR_PROG ((uint32_t)0x00000008) |
| #define | FLASH_PECR_DATA ((uint32_t)0x00000010) |
| #define | FLASH_PECR_FTDW ((uint32_t)0x00000100) |
| #define | FLASH_PECR_ERASE ((uint32_t)0x00000200) |
| #define | FLASH_PECR_FPRG ((uint32_t)0x00000400) |
| #define | FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) |
| #define | FLASH_PECR_EOPIE ((uint32_t)0x00010000) |
| #define | FLASH_PECR_ERRIE ((uint32_t)0x00020000) |
| #define | FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) |
| #define | FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_SR_BSY ((uint32_t)0x00000001) |
| #define | FLASH_SR_EOP ((uint32_t)0x00000002) |
| #define | FLASH_SR_ENHV ((uint32_t)0x00000004) |
| #define | FLASH_SR_READY ((uint32_t)0x00000008) |
| #define | FLASH_SR_WRPERR ((uint32_t)0x00000100) |
| #define | FLASH_SR_PGAERR ((uint32_t)0x00000200) |
| #define | FLASH_SR_SIZERR ((uint32_t)0x00000400) |
| #define | FLASH_SR_OPTVERR ((uint32_t)0x00000800) |
| #define | FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) |
| #define | FLASH_OBR_RDPRT ((uint16_t)0x000000AA) |
| #define | FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) |
| #define | FLASH_OBR_USER ((uint32_t)0x00700000) |
| #define | FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) |
| #define | FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) |
| #define | FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) |
| #define | FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) |
| #define | FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) |
| #define | FSMC_BCR1_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR1_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR1_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR1_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR1_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR1_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR1_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR2_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR2_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR2_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR2_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR2_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR2_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR2_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR3_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR3_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR3_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR3_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR3_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR3_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR3_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BCR4_MBKEN ((uint32_t)0x00000001) |
| #define | FSMC_BCR4_MUXEN ((uint32_t)0x00000002) |
| #define | FSMC_BCR4_MTYP ((uint32_t)0x0000000C) |
| #define | FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) |
| #define | FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) |
| #define | FSMC_BCR4_MWID ((uint32_t)0x00000030) |
| #define | FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) |
| #define | FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) |
| #define | FSMC_BCR4_FACCEN ((uint32_t)0x00000040) |
| #define | FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) |
| #define | FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) |
| #define | FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) |
| #define | FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) |
| #define | FSMC_BCR4_WREN ((uint32_t)0x00001000) |
| #define | FSMC_BCR4_WAITEN ((uint32_t)0x00002000) |
| #define | FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) |
| #define | FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) |
| #define | FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) |
| #define | FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) |
| #define | FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) |
| #define | FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) |
| #define | FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) |
| #define | FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) |
| #define | FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) |
| #define | FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) |
| #define | FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) |
| #define | FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) |
| #define | FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) |
| #define | FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) |
| #define | FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) |
| #define | FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) |
| #define | FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) |
| #define | FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) |
| #define | FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) |
| #define | FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) |
| #define | FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) |
| #define | FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) |
| #define | FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) |
| #define | FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) |
| #define | FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) |
| #define | FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) |
| #define | FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) |
| #define | FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) |
| #define | FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) |
| #define | FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) |
| #define | FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) |
| #define | FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) |
| #define | FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) |
| #define | FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) |
| #define | FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| #define | GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| #define | GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| #define | GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| #define | GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| #define | GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| #define | GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| #define | GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| #define | GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| #define | GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| #define | GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| #define | GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| #define | GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| #define | GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| #define | GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| #define | GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| #define | GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| #define | GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| #define | GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| #define | GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| #define | GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| #define | GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| #define | GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| #define | GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| #define | GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| #define | GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| #define | GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| #define | GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| #define | GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| #define | GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| #define | GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| #define | GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| #define | GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| #define | GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| #define | GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| #define | GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| #define | GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| #define | GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| #define | GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| #define | GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| #define | GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| #define | GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| #define | GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| #define | GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| #define | GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| #define | GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| #define | GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| #define | GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| #define | GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| #define | GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| #define | GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| #define | GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| #define | GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| #define | GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| #define | GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| #define | GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| #define | GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| #define | GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| #define | GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| #define | GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| #define | GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| #define | GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| #define | GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| #define | GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| #define | GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| #define | GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| #define | GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| #define | GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| #define | GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| #define | GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| #define | GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| #define | GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| #define | GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| #define | GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| #define | GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| #define | GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| #define | GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| #define | GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| #define | GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| #define | GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| #define | GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| #define | GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| #define | GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| #define | GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| #define | GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| #define | GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| #define | GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| #define | GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| #define | GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| #define | GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| #define | GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| #define | GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| #define | GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| #define | GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| #define | GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| #define | GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| #define | GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| #define | GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| #define | GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| #define | GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| #define | GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| #define | GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| #define | GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| #define | GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| #define | GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| #define | GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| #define | GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| #define | GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| #define | GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| #define | GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| #define | GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| #define | GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
| #define | GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
| #define | GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
| #define | GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
| #define | GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
| #define | GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
| #define | GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
| #define | GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
| #define | GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
| #define | GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
| #define | GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
| #define | GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
| #define | GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
| #define | GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
| #define | GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
| #define | GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
| #define | GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
| #define | GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
| #define | GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
| #define | GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
| #define | GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
| #define | GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
| #define | GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
| #define | GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
| #define | GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
| #define | GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
| #define | GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
| #define | GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
| #define | GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
| #define | GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
| #define | GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
| #define | GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
| #define | GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
| #define | GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
| #define | GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
| #define | GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
| #define | GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
| #define | GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
| #define | GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
| #define | GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
| #define | GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
| #define | GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
| #define | GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
| #define | GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
| #define | GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
| #define | GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
| #define | GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
| #define | GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
| #define | GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
| #define | GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
| #define | GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
| #define | GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
| #define | GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
| #define | GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
| #define | GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
| #define | GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
| #define | GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
| #define | GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
| #define | GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
| #define | GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
| #define | GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
| #define | GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
| #define | GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
| #define | GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| #define | GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| #define | GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| #define | GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| #define | GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| #define | GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| #define | GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| #define | GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| #define | GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| #define | GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| #define | GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| #define | GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| #define | GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| #define | GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| #define | GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| #define | GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| #define | GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| #define | GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| #define | GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| #define | GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| #define | GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| #define | GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| #define | GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| #define | GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| #define | GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| #define | GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| #define | GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| #define | GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| #define | GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| #define | GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| #define | GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| #define | GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| #define | GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| #define | GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| #define | GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| #define | GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| #define | GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| #define | GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| #define | GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| #define | GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| #define | GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| #define | GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| #define | GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| #define | GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| #define | GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| #define | GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| #define | GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| #define | GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| #define | GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| #define | GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) |
| #define | GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F) |
| #define | GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0) |
| #define | GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00) |
| #define | GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000) |
| #define | GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000) |
| #define | GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000) |
| #define | GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000) |
| #define | GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000) |
| #define | I2C_CR1_PE ((uint16_t)0x0001) |
| #define | I2C_CR1_SMBUS ((uint16_t)0x0002) |
| #define | I2C_CR1_SMBTYPE ((uint16_t)0x0008) |
| #define | I2C_CR1_ENARP ((uint16_t)0x0010) |
| #define | I2C_CR1_ENPEC ((uint16_t)0x0020) |
| #define | I2C_CR1_ENGC ((uint16_t)0x0040) |
| #define | I2C_CR1_NOSTRETCH ((uint16_t)0x0080) |
| #define | I2C_CR1_START ((uint16_t)0x0100) |
| #define | I2C_CR1_STOP ((uint16_t)0x0200) |
| #define | I2C_CR1_ACK ((uint16_t)0x0400) |
| #define | I2C_CR1_POS ((uint16_t)0x0800) |
| #define | I2C_CR1_PEC ((uint16_t)0x1000) |
| #define | I2C_CR1_ALERT ((uint16_t)0x2000) |
| #define | I2C_CR1_SWRST ((uint16_t)0x8000) |
| #define | I2C_CR2_FREQ ((uint16_t)0x003F) |
| #define | I2C_CR2_FREQ_0 ((uint16_t)0x0001) |
| #define | I2C_CR2_FREQ_1 ((uint16_t)0x0002) |
| #define | I2C_CR2_FREQ_2 ((uint16_t)0x0004) |
| #define | I2C_CR2_FREQ_3 ((uint16_t)0x0008) |
| #define | I2C_CR2_FREQ_4 ((uint16_t)0x0010) |
| #define | I2C_CR2_FREQ_5 ((uint16_t)0x0020) |
| #define | I2C_CR2_ITERREN ((uint16_t)0x0100) |
| #define | I2C_CR2_ITEVTEN ((uint16_t)0x0200) |
| #define | I2C_CR2_ITBUFEN ((uint16_t)0x0400) |
| #define | I2C_CR2_DMAEN ((uint16_t)0x0800) |
| #define | I2C_CR2_LAST ((uint16_t)0x1000) |
| #define | I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) |
| #define | I2C_OAR1_ADD8_9 ((uint16_t)0x0300) |
| #define | I2C_OAR1_ADD0 ((uint16_t)0x0001) |
| #define | I2C_OAR1_ADD1 ((uint16_t)0x0002) |
| #define | I2C_OAR1_ADD2 ((uint16_t)0x0004) |
| #define | I2C_OAR1_ADD3 ((uint16_t)0x0008) |
| #define | I2C_OAR1_ADD4 ((uint16_t)0x0010) |
| #define | I2C_OAR1_ADD5 ((uint16_t)0x0020) |
| #define | I2C_OAR1_ADD6 ((uint16_t)0x0040) |
| #define | I2C_OAR1_ADD7 ((uint16_t)0x0080) |
| #define | I2C_OAR1_ADD8 ((uint16_t)0x0100) |
| #define | I2C_OAR1_ADD9 ((uint16_t)0x0200) |
| #define | I2C_OAR1_ADDMODE ((uint16_t)0x8000) |
| #define | I2C_OAR2_ENDUAL ((uint8_t)0x01) |
| #define | I2C_OAR2_ADD2 ((uint8_t)0xFE) |
| #define | I2C_DR_DR ((uint8_t)0xFF) |
| #define | I2C_SR1_SB ((uint16_t)0x0001) |
| #define | I2C_SR1_ADDR ((uint16_t)0x0002) |
| #define | I2C_SR1_BTF ((uint16_t)0x0004) |
| #define | I2C_SR1_ADD10 ((uint16_t)0x0008) |
| #define | I2C_SR1_STOPF ((uint16_t)0x0010) |
| #define | I2C_SR1_RXNE ((uint16_t)0x0040) |
| #define | I2C_SR1_TXE ((uint16_t)0x0080) |
| #define | I2C_SR1_BERR ((uint16_t)0x0100) |
| #define | I2C_SR1_ARLO ((uint16_t)0x0200) |
| #define | I2C_SR1_AF ((uint16_t)0x0400) |
| #define | I2C_SR1_OVR ((uint16_t)0x0800) |
| #define | I2C_SR1_PECERR ((uint16_t)0x1000) |
| #define | I2C_SR1_TIMEOUT ((uint16_t)0x4000) |
| #define | I2C_SR1_SMBALERT ((uint16_t)0x8000) |
| #define | I2C_SR2_MSL ((uint16_t)0x0001) |
| #define | I2C_SR2_BUSY ((uint16_t)0x0002) |
| #define | I2C_SR2_TRA ((uint16_t)0x0004) |
| #define | I2C_SR2_GENCALL ((uint16_t)0x0010) |
| #define | I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) |
| #define | I2C_SR2_SMBHOST ((uint16_t)0x0040) |
| #define | I2C_SR2_DUALF ((uint16_t)0x0080) |
| #define | I2C_SR2_PEC ((uint16_t)0xFF00) |
| #define | I2C_CCR_CCR ((uint16_t)0x0FFF) |
| #define | I2C_CCR_DUTY ((uint16_t)0x4000) |
| #define | I2C_CCR_FS ((uint16_t)0x8000) |
| #define | I2C_TRISE_TRISE ((uint8_t)0x3F) |
| #define | IWDG_KR_KEY ((uint16_t)0xFFFF) |
| #define | IWDG_PR_PR ((uint8_t)0x07) |
| #define | IWDG_PR_PR_0 ((uint8_t)0x01) |
| #define | IWDG_PR_PR_1 ((uint8_t)0x02) |
| #define | IWDG_PR_PR_2 ((uint8_t)0x04) |
| #define | IWDG_RLR_RL ((uint16_t)0x0FFF) |
| #define | IWDG_SR_PVU ((uint8_t)0x01) |
| #define | IWDG_SR_RVU ((uint8_t)0x02) |
| #define | LCD_CR_LCDEN ((uint32_t)0x00000001) |
| #define | LCD_CR_VSEL ((uint32_t)0x00000002) |
| #define | LCD_CR_DUTY ((uint32_t)0x0000001C) |
| #define | LCD_CR_DUTY_0 ((uint32_t)0x00000004) |
| #define | LCD_CR_DUTY_1 ((uint32_t)0x00000008) |
| #define | LCD_CR_DUTY_2 ((uint32_t)0x00000010) |
| #define | LCD_CR_BIAS ((uint32_t)0x00000060) |
| #define | LCD_CR_BIAS_0 ((uint32_t)0x00000020) |
| #define | LCD_CR_BIAS_1 ((uint32_t)0x00000040) |
| #define | LCD_CR_MUX_SEG ((uint32_t)0x00000080) |
| #define | LCD_FCR_HD ((uint32_t)0x00000001) |
| #define | LCD_FCR_SOFIE ((uint32_t)0x00000002) |
| #define | LCD_FCR_UDDIE ((uint32_t)0x00000008) |
| #define | LCD_FCR_PON ((uint32_t)0x00000070) |
| #define | LCD_FCR_PON_0 ((uint32_t)0x00000010) |
| #define | LCD_FCR_PON_1 ((uint32_t)0x00000020) |
| #define | LCD_FCR_PON_2 ((uint32_t)0x00000040) |
| #define | LCD_FCR_DEAD ((uint32_t)0x00000380) |
| #define | LCD_FCR_DEAD_0 ((uint32_t)0x00000080) |
| #define | LCD_FCR_DEAD_1 ((uint32_t)0x00000100) |
| #define | LCD_FCR_DEAD_2 ((uint32_t)0x00000200) |
| #define | LCD_FCR_CC ((uint32_t)0x00001C00) |
| #define | LCD_FCR_CC_0 ((uint32_t)0x00000400) |
| #define | LCD_FCR_CC_1 ((uint32_t)0x00000800) |
| #define | LCD_FCR_CC_2 ((uint32_t)0x00001000) |
| #define | LCD_FCR_BLINKF ((uint32_t)0x0000E000) |
| #define | LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) |
| #define | LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) |
| #define | LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) |
| #define | LCD_FCR_BLINK ((uint32_t)0x00030000) |
| #define | LCD_FCR_BLINK_0 ((uint32_t)0x00010000) |
| #define | LCD_FCR_BLINK_1 ((uint32_t)0x00020000) |
| #define | LCD_FCR_DIV ((uint32_t)0x003C0000) |
| #define | LCD_FCR_PS ((uint32_t)0x03C00000) |
| #define | LCD_SR_ENS ((uint32_t)0x00000001) |
| #define | LCD_SR_SOF ((uint32_t)0x00000002) |
| #define | LCD_SR_UDR ((uint32_t)0x00000004) |
| #define | LCD_SR_UDD ((uint32_t)0x00000008) |
| #define | LCD_SR_RDY ((uint32_t)0x00000010) |
| #define | LCD_SR_FCRSR ((uint32_t)0x00000020) |
| #define | LCD_CLR_SOFC ((uint32_t)0x00000002) |
| #define | LCD_CLR_UDDC ((uint32_t)0x00000008) |
| #define | LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) |
| #define | PWR_CR_LPSDSR ((uint16_t)0x0001) |
| #define | PWR_CR_PDDS ((uint16_t)0x0002) |
| #define | PWR_CR_CWUF ((uint16_t)0x0004) |
| #define | PWR_CR_CSBF ((uint16_t)0x0008) |
| #define | PWR_CR_PVDE ((uint16_t)0x0010) |
| #define | PWR_CR_PLS ((uint16_t)0x00E0) |
| #define | PWR_CR_PLS_0 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_1 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_2 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV0 ((uint16_t)0x0000) |
| #define | PWR_CR_PLS_LEV1 ((uint16_t)0x0020) |
| #define | PWR_CR_PLS_LEV2 ((uint16_t)0x0040) |
| #define | PWR_CR_PLS_LEV3 ((uint16_t)0x0060) |
| #define | PWR_CR_PLS_LEV4 ((uint16_t)0x0080) |
| #define | PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) |
| #define | PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) |
| #define | PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) |
| #define | PWR_CR_DBP ((uint16_t)0x0100) |
| #define | PWR_CR_ULP ((uint16_t)0x0200) |
| #define | PWR_CR_FWU ((uint16_t)0x0400) |
| #define | PWR_CR_VOS ((uint16_t)0x1800) |
| #define | PWR_CR_VOS_0 ((uint16_t)0x0800) |
| #define | PWR_CR_VOS_1 ((uint16_t)0x1000) |
| #define | PWR_CR_LPRUN ((uint16_t)0x4000) |
| #define | PWR_CSR_WUF ((uint16_t)0x0001) |
| #define | PWR_CSR_SBF ((uint16_t)0x0002) |
| #define | PWR_CSR_PVDO ((uint16_t)0x0004) |
| #define | PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) |
| #define | PWR_CSR_VOSF ((uint16_t)0x0010) |
| #define | PWR_CSR_REGLPF ((uint16_t)0x0020) |
| #define | PWR_CSR_EWUP1 ((uint16_t)0x0100) |
| #define | PWR_CSR_EWUP2 ((uint16_t)0x0200) |
| #define | PWR_CSR_EWUP3 ((uint16_t)0x0400) |
| #define | RCC_CR_HSION ((uint32_t)0x00000001) |
| #define | RCC_CR_HSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CR_MSION ((uint32_t)0x00000100) |
| #define | RCC_CR_MSIRDY ((uint32_t)0x00000200) |
| #define | RCC_CR_HSEON ((uint32_t)0x00010000) |
| #define | RCC_CR_HSERDY ((uint32_t)0x00020000) |
| #define | RCC_CR_HSEBYP ((uint32_t)0x00040000) |
| #define | RCC_CR_PLLON ((uint32_t)0x01000000) |
| #define | RCC_CR_PLLRDY ((uint32_t)0x02000000) |
| #define | RCC_CR_CSSON ((uint32_t)0x10000000) |
| #define | RCC_CR_RTCPRE ((uint32_t)0x60000000) |
| #define | RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) |
| #define | RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) |
| #define | RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) |
| #define | RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) |
| #define | RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) |
| #define | RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) |
| #define | RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) |
| #define | RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) |
| #define | RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) |
| #define | RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) |
| #define | RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) |
| #define | RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) |
| #define | RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) |
| #define | RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) |
| #define | RCC_CFGR_SW ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SW_0 ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_1 ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_MSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SW_HSI ((uint32_t)0x00000001) |
| #define | RCC_CFGR_SW_HSE ((uint32_t)0x00000002) |
| #define | RCC_CFGR_SW_PLL ((uint32_t)0x00000003) |
| #define | RCC_CFGR_SWS ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_SWS_0 ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_1 ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) |
| #define | RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) |
| #define | RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) |
| #define | RCC_CFGR_HPRE ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) |
| #define | RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) |
| #define | RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) |
| #define | RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) |
| #define | RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) |
| #define | RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) |
| #define | RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) |
| #define | RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) |
| #define | RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) |
| #define | RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) |
| #define | RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) |
| #define | RCC_CFGR_PPRE1 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) |
| #define | RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) |
| #define | RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) |
| #define | RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) |
| #define | RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) |
| #define | RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) |
| #define | RCC_CFGR_PPRE2 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) |
| #define | RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) |
| #define | RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) |
| #define | RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) |
| #define | RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) |
| #define | RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) |
| #define | RCC_CFGR_PLLSRC ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) |
| #define | RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) |
| #define | RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) |
| #define | RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) |
| #define | RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) |
| #define | RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) |
| #define | RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) |
| #define | RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) |
| #define | RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) |
| #define | RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) |
| #define | RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) |
| #define | RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) |
| #define | RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) |
| #define | RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) |
| #define | RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) |
| #define | RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) |
| #define | RCC_CFGR_MCOSEL ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) |
| #define | RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) |
| #define | RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) |
| #define | RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) |
| #define | RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) |
| #define | RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) |
| #define | RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) |
| #define | RCC_CFGR_MCOPRE ((uint32_t)0x70000000) |
| #define | RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) |
| #define | RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) |
| #define | RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) |
| #define | RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) |
| #define | RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) |
| #define | RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) |
| #define | RCC_CIR_LSIRDYF ((uint32_t)0x00000001) |
| #define | RCC_CIR_LSERDYF ((uint32_t)0x00000002) |
| #define | RCC_CIR_HSIRDYF ((uint32_t)0x00000004) |
| #define | RCC_CIR_HSERDYF ((uint32_t)0x00000008) |
| #define | RCC_CIR_PLLRDYF ((uint32_t)0x00000010) |
| #define | RCC_CIR_MSIRDYF ((uint32_t)0x00000020) |
| #define | RCC_CIR_LSECSS ((uint32_t)0x00000040) |
| #define | RCC_CIR_CSSF ((uint32_t)0x00000080) |
| #define | RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) |
| #define | RCC_CIR_LSERDYIE ((uint32_t)0x00000200) |
| #define | RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) |
| #define | RCC_CIR_HSERDYIE ((uint32_t)0x00000800) |
| #define | RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) |
| #define | RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) |
| #define | RCC_CIR_LSECSSIE ((uint32_t)0x00004000) |
| #define | RCC_CIR_LSIRDYC ((uint32_t)0x00010000) |
| #define | RCC_CIR_LSERDYC ((uint32_t)0x00020000) |
| #define | RCC_CIR_HSIRDYC ((uint32_t)0x00040000) |
| #define | RCC_CIR_HSERDYC ((uint32_t)0x00080000) |
| #define | RCC_CIR_PLLRDYC ((uint32_t)0x00100000) |
| #define | RCC_CIR_MSIRDYC ((uint32_t)0x00200000) |
| #define | RCC_CIR_LSECSSC ((uint32_t)0x00400000) |
| #define | RCC_CIR_CSSC ((uint32_t)0x00800000) |
| #define | RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) |
| #define | RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) |
| #define | RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) |
| #define | RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) |
| #define | RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) |
| #define | RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) |
| #define | RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) |
| #define | RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) |
| #define | RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) |
| #define | RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) |
| #define | RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) |
| #define | RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) |
| #define | RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) |
| #define | RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) |
| #define | RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) |
| #define | RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) |
| #define | RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) |
| #define | RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) |
| #define | RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) |
| #define | RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) |
| #define | RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| #define | RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) |
| #define | RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) |
| #define | RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) |
| #define | RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) |
| #define | RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) |
| #define | RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) |
| #define | RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) |
| #define | RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) |
| #define | RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) |
| #define | RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) |
| #define | RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) |
| #define | RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) |
| #define | RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) |
| #define | RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) |
| #define | RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) |
| #define | RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) |
| #define | RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) |
| #define | RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) |
| #define | RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) |
| #define | RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) |
| #define | RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) |
| #define | RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) |
| #define | RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) |
| #define | RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) |
| #define | RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) |
| #define | RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) |
| #define | RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) |
| #define | RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) |
| #define | RCC_AHBENR_CRCEN ((uint32_t)0x00001000) |
| #define | RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) |
| #define | RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) |
| #define | RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) |
| #define | RCC_AHBENR_AESEN ((uint32_t)0x08000000) |
| #define | RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) |
| #define | RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) |
| #define | RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) |
| #define | RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) |
| #define | RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) |
| #define | RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) |
| #define | RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) |
| #define | RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| #define | RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) |
| #define | RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) |
| #define | RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) |
| #define | RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) |
| #define | RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) |
| #define | RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) |
| #define | RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) |
| #define | RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) |
| #define | RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) |
| #define | RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) |
| #define | RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) |
| #define | RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) |
| #define | RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) |
| #define | RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) |
| #define | RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) |
| #define | RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) |
| #define | RCC_APB1ENR_USBEN ((uint32_t)0x00800000) |
| #define | RCC_APB1ENR_PWREN ((uint32_t)0x10000000) |
| #define | RCC_APB1ENR_DACEN ((uint32_t)0x20000000) |
| #define | RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) |
| #define | RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) |
| #define | RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) |
| #define | RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) |
| #define | RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) |
| #define | RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) |
| #define | RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) |
| #define | RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) |
| #define | RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) |
| #define | RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) |
| #define | RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) |
| #define | RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) |
| #define | RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) |
| #define | RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) |
| #define | RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) |
| #define | RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) |
| #define | RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) |
| #define | RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) |
| #define | RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) |
| #define | RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) |
| #define | RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) |
| #define | RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) |
| #define | RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) |
| #define | RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) |
| #define | RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) |
| #define | RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) |
| #define | RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) |
| #define | RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) |
| #define | RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) |
| #define | RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) |
| #define | RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) |
| #define | RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) |
| #define | RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) |
| #define | RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) |
| #define | RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) |
| #define | RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) |
| #define | RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) |
| #define | RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) |
| #define | RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) |
| #define | RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) |
| #define | RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) |
| #define | RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) |
| #define | RCC_CSR_LSION ((uint32_t)0x00000001) |
| #define | RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| #define | RCC_CSR_LSEON ((uint32_t)0x00000100) |
| #define | RCC_CSR_LSERDY ((uint32_t)0x00000200) |
| #define | RCC_CSR_LSEBYP ((uint32_t)0x00000400) |
| #define | RCC_CSR_LSECSSON ((uint32_t)0x00000800) |
| #define | RCC_CSR_LSECSSD ((uint32_t)0x00001000) |
| #define | RCC_CSR_RTCSEL ((uint32_t)0x00030000) |
| #define | RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) |
| #define | RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) |
| #define | RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) |
| #define | RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) |
| #define | RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) |
| #define | RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) |
| #define | RCC_CSR_RTCEN ((uint32_t)0x00400000) |
| #define | RCC_CSR_RTCRST ((uint32_t)0x00800000) |
| #define | RCC_CSR_RMVF ((uint32_t)0x01000000) |
| #define | RCC_CSR_OBLRSTF ((uint32_t)0x02000000) |
| #define | RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| #define | RCC_CSR_PORRSTF ((uint32_t)0x08000000) |
| #define | RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| #define | RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| #define | RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| #define | RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| #define | RTC_TR_PM ((uint32_t)0x00400000) |
| #define | RTC_TR_HT ((uint32_t)0x00300000) |
| #define | RTC_TR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TR_ST ((uint32_t)0x00000070) |
| #define | RTC_TR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_DR_YT ((uint32_t)0x00F00000) |
| #define | RTC_DR_YT_0 ((uint32_t)0x00100000) |
| #define | RTC_DR_YT_1 ((uint32_t)0x00200000) |
| #define | RTC_DR_YT_2 ((uint32_t)0x00400000) |
| #define | RTC_DR_YT_3 ((uint32_t)0x00800000) |
| #define | RTC_DR_YU ((uint32_t)0x000F0000) |
| #define | RTC_DR_YU_0 ((uint32_t)0x00010000) |
| #define | RTC_DR_YU_1 ((uint32_t)0x00020000) |
| #define | RTC_DR_YU_2 ((uint32_t)0x00040000) |
| #define | RTC_DR_YU_3 ((uint32_t)0x00080000) |
| #define | RTC_DR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_DR_MT ((uint32_t)0x00001000) |
| #define | RTC_DR_MU ((uint32_t)0x00000F00) |
| #define | RTC_DR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_DR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_DR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_DR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_DR_DT ((uint32_t)0x00000030) |
| #define | RTC_DR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_DR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_DR_DU ((uint32_t)0x0000000F) |
| #define | RTC_DR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_DR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_DR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_DR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_CR_COE ((uint32_t)0x00800000) |
| #define | RTC_CR_OSEL ((uint32_t)0x00600000) |
| #define | RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| #define | RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| #define | RTC_CR_POL ((uint32_t)0x00100000) |
| #define | RTC_CR_COSEL ((uint32_t)0x00080000) |
| #define | RTC_CR_BCK ((uint32_t)0x00040000) |
| #define | RTC_CR_SUB1H ((uint32_t)0x00020000) |
| #define | RTC_CR_ADD1H ((uint32_t)0x00010000) |
| #define | RTC_CR_TSIE ((uint32_t)0x00008000) |
| #define | RTC_CR_WUTIE ((uint32_t)0x00004000) |
| #define | RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| #define | RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| #define | RTC_CR_TSE ((uint32_t)0x00000800) |
| #define | RTC_CR_WUTE ((uint32_t)0x00000400) |
| #define | RTC_CR_ALRBE ((uint32_t)0x00000200) |
| #define | RTC_CR_ALRAE ((uint32_t)0x00000100) |
| #define | RTC_CR_DCE ((uint32_t)0x00000080) |
| #define | RTC_CR_FMT ((uint32_t)0x00000040) |
| #define | RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| #define | RTC_CR_REFCKON ((uint32_t)0x00000010) |
| #define | RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| #define | RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| #define | RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| #define | RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| #define | RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| #define | RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| #define | RTC_ISR_TAMP3F ((uint32_t)0x00008000) |
| #define | RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
| #define | RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| #define | RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| #define | RTC_ISR_TSF ((uint32_t)0x00000800) |
| #define | RTC_ISR_WUTF ((uint32_t)0x00000400) |
| #define | RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| #define | RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| #define | RTC_ISR_INIT ((uint32_t)0x00000080) |
| #define | RTC_ISR_INITF ((uint32_t)0x00000040) |
| #define | RTC_ISR_RSF ((uint32_t)0x00000020) |
| #define | RTC_ISR_INITS ((uint32_t)0x00000010) |
| #define | RTC_ISR_SHPF ((uint32_t)0x00000008) |
| #define | RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| #define | RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| #define | RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| #define | RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| #define | RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) |
| #define | RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| #define | RTC_CALIBR_DCS ((uint32_t)0x00000080) |
| #define | RTC_CALIBR_DC ((uint32_t)0x0000001F) |
| #define | RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| #define | RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| #define | RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| #define | RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| #define | RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| #define | RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| #define | RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| #define | RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| #define | RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| #define | RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| #define | RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| #define | RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| #define | RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| #define | RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| #define | RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_WPR_KEY ((uint32_t)0x000000FF) |
| #define | RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| #define | RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| #define | RTC_TSTR_PM ((uint32_t)0x00400000) |
| #define | RTC_TSTR_HT ((uint32_t)0x00300000) |
| #define | RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| #define | RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| #define | RTC_TSTR_HU ((uint32_t)0x000F0000) |
| #define | RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| #define | RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| #define | RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| #define | RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| #define | RTC_TSTR_MNT ((uint32_t)0x00007000) |
| #define | RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| #define | RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| #define | RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| #define | RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| #define | RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSTR_ST ((uint32_t)0x00000070) |
| #define | RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| #define | RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| #define | RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| #define | RTC_TSTR_SU ((uint32_t)0x0000000F) |
| #define | RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| #define | RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| #define | RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| #define | RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| #define | RTC_TSDR_MT ((uint32_t)0x00001000) |
| #define | RTC_TSDR_MU ((uint32_t)0x00000F00) |
| #define | RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| #define | RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| #define | RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| #define | RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| #define | RTC_TSDR_DT ((uint32_t)0x00000030) |
| #define | RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| #define | RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| #define | RTC_TSDR_DU ((uint32_t)0x0000000F) |
| #define | RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| #define | RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| #define | RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| #define | RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| #define | RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| #define | RTC_CALR_CALP ((uint32_t)0x00008000) |
| #define | RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| #define | RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| #define | RTC_CALR_CALM ((uint32_t)0x000001FF) |
| #define | RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| #define | RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| #define | RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| #define | RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| #define | RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| #define | RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| #define | RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| #define | RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| #define | RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
| #define | RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
| #define | RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
| #define | RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| #define | RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| #define | RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
| #define | RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| #define | RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| #define | RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
| #define | RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| #define | RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| #define | RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| #define | RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
| #define | RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) |
| #define | RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) |
| #define | RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) |
| #define | RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
| #define | RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
| #define | RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
| #define | RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
| #define | RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| #define | RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| #define | RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| #define | RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| #define | RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| #define | RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| #define | RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP20R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP21R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP22R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP23R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP24R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP25R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP26R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP27R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP28R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP29R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP30R ((uint32_t)0xFFFFFFFF) |
| #define | RTC_BKP31R ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_POWER_PWRCTRL ((uint8_t)0x03) |
| #define | SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) |
| #define | SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) |
| #define | SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) |
| #define | SDIO_CLKCR_CLKEN ((uint16_t)0x0100) |
| #define | SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) |
| #define | SDIO_CLKCR_BYPASS ((uint16_t)0x0400) |
| #define | SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) |
| #define | SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) |
| #define | SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) |
| #define | SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) |
| #define | SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) |
| #define | SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_CMD_CMDINDEX ((uint16_t)0x003F) |
| #define | SDIO_CMD_WAITRESP ((uint16_t)0x00C0) |
| #define | SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) |
| #define | SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) |
| #define | SDIO_CMD_WAITINT ((uint16_t)0x0100) |
| #define | SDIO_CMD_WAITPEND ((uint16_t)0x0200) |
| #define | SDIO_CMD_CPSMEN ((uint16_t)0x0400) |
| #define | SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) |
| #define | SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) |
| #define | SDIO_CMD_NIEN ((uint16_t)0x2000) |
| #define | SDIO_CMD_CEATACMD ((uint16_t)0x4000) |
| #define | SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) |
| #define | SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) |
| #define | SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) |
| #define | SDIO_DCTRL_DTEN ((uint16_t)0x0001) |
| #define | SDIO_DCTRL_DTDIR ((uint16_t)0x0002) |
| #define | SDIO_DCTRL_DTMODE ((uint16_t)0x0004) |
| #define | SDIO_DCTRL_DMAEN ((uint16_t)0x0008) |
| #define | SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) |
| #define | SDIO_DCTRL_RWSTART ((uint16_t)0x0100) |
| #define | SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) |
| #define | SDIO_DCTRL_RWMOD ((uint16_t)0x0400) |
| #define | SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) |
| #define | SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) |
| #define | SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) |
| #define | SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) |
| #define | SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) |
| #define | SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) |
| #define | SDIO_STA_TXUNDERR ((uint32_t)0x00000010) |
| #define | SDIO_STA_RXOVERR ((uint32_t)0x00000020) |
| #define | SDIO_STA_CMDREND ((uint32_t)0x00000040) |
| #define | SDIO_STA_CMDSENT ((uint32_t)0x00000080) |
| #define | SDIO_STA_DATAEND ((uint32_t)0x00000100) |
| #define | SDIO_STA_STBITERR ((uint32_t)0x00000200) |
| #define | SDIO_STA_DBCKEND ((uint32_t)0x00000400) |
| #define | SDIO_STA_CMDACT ((uint32_t)0x00000800) |
| #define | SDIO_STA_TXACT ((uint32_t)0x00001000) |
| #define | SDIO_STA_RXACT ((uint32_t)0x00002000) |
| #define | SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) |
| #define | SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) |
| #define | SDIO_STA_TXFIFOF ((uint32_t)0x00010000) |
| #define | SDIO_STA_RXFIFOF ((uint32_t)0x00020000) |
| #define | SDIO_STA_TXFIFOE ((uint32_t)0x00040000) |
| #define | SDIO_STA_RXFIFOE ((uint32_t)0x00080000) |
| #define | SDIO_STA_TXDAVL ((uint32_t)0x00100000) |
| #define | SDIO_STA_RXDAVL ((uint32_t)0x00200000) |
| #define | SDIO_STA_SDIOIT ((uint32_t)0x00400000) |
| #define | SDIO_STA_CEATAEND ((uint32_t)0x00800000) |
| #define | SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) |
| #define | SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) |
| #define | SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) |
| #define | SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) |
| #define | SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) |
| #define | SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) |
| #define | SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) |
| #define | SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) |
| #define | SDIO_ICR_DATAENDC ((uint32_t)0x00000100) |
| #define | SDIO_ICR_STBITERRC ((uint32_t)0x00000200) |
| #define | SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) |
| #define | SDIO_ICR_SDIOITC ((uint32_t)0x00400000) |
| #define | SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) |
| #define | SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) |
| #define | SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) |
| #define | SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) |
| #define | SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) |
| #define | SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) |
| #define | SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) |
| #define | SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) |
| #define | SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) |
| #define | SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) |
| #define | SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) |
| #define | SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) |
| #define | SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) |
| #define | SDIO_MASK_TXACTIE ((uint32_t)0x00001000) |
| #define | SDIO_MASK_RXACTIE ((uint32_t)0x00002000) |
| #define | SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) |
| #define | SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) |
| #define | SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) |
| #define | SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) |
| #define | SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) |
| #define | SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) |
| #define | SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) |
| #define | SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) |
| #define | SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) |
| #define | SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) |
| #define | SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) |
| #define | SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) |
| #define | SPI_CR1_CPHA ((uint16_t)0x0001) |
| #define | SPI_CR1_CPOL ((uint16_t)0x0002) |
| #define | SPI_CR1_MSTR ((uint16_t)0x0004) |
| #define | SPI_CR1_BR ((uint16_t)0x0038) |
| #define | SPI_CR1_BR_0 ((uint16_t)0x0008) |
| #define | SPI_CR1_BR_1 ((uint16_t)0x0010) |
| #define | SPI_CR1_BR_2 ((uint16_t)0x0020) |
| #define | SPI_CR1_SPE ((uint16_t)0x0040) |
| #define | SPI_CR1_LSBFIRST ((uint16_t)0x0080) |
| #define | SPI_CR1_SSI ((uint16_t)0x0100) |
| #define | SPI_CR1_SSM ((uint16_t)0x0200) |
| #define | SPI_CR1_RXONLY ((uint16_t)0x0400) |
| #define | SPI_CR1_DFF ((uint16_t)0x0800) |
| #define | SPI_CR1_CRCNEXT ((uint16_t)0x1000) |
| #define | SPI_CR1_CRCEN ((uint16_t)0x2000) |
| #define | SPI_CR1_BIDIOE ((uint16_t)0x4000) |
| #define | SPI_CR1_BIDIMODE ((uint16_t)0x8000) |
| #define | SPI_CR2_RXDMAEN ((uint8_t)0x01) |
| #define | SPI_CR2_TXDMAEN ((uint8_t)0x02) |
| #define | SPI_CR2_SSOE ((uint8_t)0x04) |
| #define | SPI_CR2_FRF ((uint8_t)0x08) |
| #define | SPI_CR2_ERRIE ((uint8_t)0x20) |
| #define | SPI_CR2_RXNEIE ((uint8_t)0x40) |
| #define | SPI_CR2_TXEIE ((uint8_t)0x80) |
| #define | SPI_SR_RXNE ((uint8_t)0x01) |
| #define | SPI_SR_TXE ((uint8_t)0x02) |
| #define | SPI_SR_CHSIDE ((uint8_t)0x04) |
| #define | SPI_SR_UDR ((uint8_t)0x08) |
| #define | SPI_SR_CRCERR ((uint8_t)0x10) |
| #define | SPI_SR_MODF ((uint8_t)0x20) |
| #define | SPI_SR_OVR ((uint8_t)0x40) |
| #define | SPI_SR_BSY ((uint8_t)0x80) |
| #define | SPI_DR_DR ((uint16_t)0xFFFF) |
| #define | SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) |
| #define | SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) |
| #define | SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) |
| #define | SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) |
| #define | SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) |
| #define | SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) |
| #define | SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) |
| #define | SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) |
| #define | SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) |
| #define | SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) |
| #define | SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) |
| #define | SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) |
| #define | SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) |
| #define | SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) |
| #define | SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) |
| #define | SPI_I2SCFGR_I2SE ((uint16_t)0x0400) |
| #define | SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) |
| #define | SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) |
| #define | SPI_I2SPR_ODD ((uint16_t)0x0100) |
| #define | SPI_I2SPR_MCKOE ((uint16_t)0x0200) |
| #define | SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) |
| #define | SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
| #define | SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
| #define | SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) |
| #define | SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) |
| #define | SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) |
| #define | SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) |
| #define | SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) |
| EXTI0 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) |
| #define | SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) |
| EXTI1 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) |
| #define | SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) |
| EXTI2 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) |
| #define | SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) |
| EXTI3 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) |
| EXTI4 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) |
| EXTI5 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) |
| EXTI6 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) |
| EXTI7 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) |
| EXTI8 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) |
| EXTI9 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) |
| EXTI10 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) |
| EXTI11 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) |
| #define | SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) |
| #define | SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) |
| #define | SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) |
| #define | SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) |
| #define | SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) |
| EXTI12 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) |
| #define | SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) |
| #define | SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) |
| #define | SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) |
| #define | SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) |
| #define | SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) |
| #define | SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) |
| EXTI13 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) |
| #define | SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) |
| #define | SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) |
| #define | SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) |
| #define | SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) |
| #define | SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) |
| #define | SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) |
| EXTI14 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) |
| #define | SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) |
| #define | SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) |
| #define | SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) |
| #define | SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) |
| #define | SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) |
| #define | SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) |
| EXTI15 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) |
| #define | SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) |
| #define | SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) |
| #define | SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) |
| #define | SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) |
| #define | SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) |
| #define | RI_ICR_IC1Z ((uint32_t)0x0000000F) |
| #define | RI_ICR_IC1Z_0 ((uint32_t)0x00000001) |
| #define | RI_ICR_IC1Z_1 ((uint32_t)0x00000002) |
| #define | RI_ICR_IC1Z_2 ((uint32_t)0x00000004) |
| #define | RI_ICR_IC1Z_3 ((uint32_t)0x00000008) |
| #define | RI_ICR_IC2Z ((uint32_t)0x000000F0) |
| #define | RI_ICR_IC2Z_0 ((uint32_t)0x00000010) |
| #define | RI_ICR_IC2Z_1 ((uint32_t)0x00000020) |
| #define | RI_ICR_IC2Z_2 ((uint32_t)0x00000040) |
| #define | RI_ICR_IC2Z_3 ((uint32_t)0x00000080) |
| #define | RI_ICR_IC3Z ((uint32_t)0x00000F00) |
| #define | RI_ICR_IC3Z_0 ((uint32_t)0x00000100) |
| #define | RI_ICR_IC3Z_1 ((uint32_t)0x00000200) |
| #define | RI_ICR_IC3Z_2 ((uint32_t)0x00000400) |
| #define | RI_ICR_IC3Z_3 ((uint32_t)0x00000800) |
| #define | RI_ICR_IC4Z ((uint32_t)0x0000F000) |
| #define | RI_ICR_IC4Z_0 ((uint32_t)0x00001000) |
| #define | RI_ICR_IC4Z_1 ((uint32_t)0x00002000) |
| #define | RI_ICR_IC4Z_2 ((uint32_t)0x00004000) |
| #define | RI_ICR_IC4Z_3 ((uint32_t)0x00008000) |
| #define | RI_ICR_TIM ((uint32_t)0x00030000) |
| #define | RI_ICR_TIM_0 ((uint32_t)0x00010000) |
| #define | RI_ICR_TIM_1 ((uint32_t)0x00020000) |
| #define | RI_ICR_IC1 ((uint32_t)0x00040000) |
| #define | RI_ICR_IC2 ((uint32_t)0x00080000) |
| #define | RI_ICR_IC3 ((uint32_t)0x00100000) |
| #define | RI_ICR_IC4 ((uint32_t)0x00200000) |
| #define | RI_ASCR1_CH ((uint32_t)0x03FCFFFF) |
| #define | RI_ASCR1_CH_0 ((uint32_t)0x00000001) |
| #define | RI_ASCR1_CH_1 ((uint32_t)0x00000002) |
| #define | RI_ASCR1_CH_2 ((uint32_t)0x00000004) |
| #define | RI_ASCR1_CH_3 ((uint32_t)0x00000008) |
| #define | RI_ASCR1_CH_4 ((uint32_t)0x00000010) |
| #define | RI_ASCR1_CH_5 ((uint32_t)0x00000020) |
| #define | RI_ASCR1_CH_6 ((uint32_t)0x00000040) |
| #define | RI_ASCR1_CH_7 ((uint32_t)0x00000080) |
| #define | RI_ASCR1_CH_8 ((uint32_t)0x00000100) |
| #define | RI_ASCR1_CH_9 ((uint32_t)0x00000200) |
| #define | RI_ASCR1_CH_10 ((uint32_t)0x00000400) |
| #define | RI_ASCR1_CH_11 ((uint32_t)0x00000800) |
| #define | RI_ASCR1_CH_12 ((uint32_t)0x00001000) |
| #define | RI_ASCR1_CH_13 ((uint32_t)0x00002000) |
| #define | RI_ASCR1_CH_14 ((uint32_t)0x00004000) |
| #define | RI_ASCR1_CH_15 ((uint32_t)0x00008000) |
| #define | RI_ASCR1_CH_31 ((uint32_t)0x00010000) |
| #define | RI_ASCR1_CH_18 ((uint32_t)0x00040000) |
| #define | RI_ASCR1_CH_19 ((uint32_t)0x00080000) |
| #define | RI_ASCR1_CH_20 ((uint32_t)0x00100000) |
| #define | RI_ASCR1_CH_21 ((uint32_t)0x00200000) |
| #define | RI_ASCR1_CH_22 ((uint32_t)0x00400000) |
| #define | RI_ASCR1_CH_23 ((uint32_t)0x00800000) |
| #define | RI_ASCR1_CH_24 ((uint32_t)0x01000000) |
| #define | RI_ASCR1_CH_25 ((uint32_t)0x02000000) |
| #define | RI_ASCR1_VCOMP ((uint32_t)0x04000000) |
| #define | RI_ASCR1_CH_27 ((uint32_t)0x00400000) |
| #define | RI_ASCR1_CH_28 ((uint32_t)0x00800000) |
| #define | RI_ASCR1_CH_29 ((uint32_t)0x01000000) |
| #define | RI_ASCR1_CH_30 ((uint32_t)0x02000000) |
| #define | RI_ASCR1_SCM ((uint32_t)0x80000000) |
| #define | RI_ASCR2_GR10_1 ((uint32_t)0x00000001) |
| #define | RI_ASCR2_GR10_2 ((uint32_t)0x00000002) |
| #define | RI_ASCR2_GR10_3 ((uint32_t)0x00000004) |
| #define | RI_ASCR2_GR10_4 ((uint32_t)0x00000008) |
| #define | RI_ASCR2_GR6_1 ((uint32_t)0x00000010) |
| #define | RI_ASCR2_GR6_2 ((uint32_t)0x00000020) |
| #define | RI_ASCR2_GR5_1 ((uint32_t)0x00000040) |
| #define | RI_ASCR2_GR5_2 ((uint32_t)0x00000080) |
| #define | RI_ASCR2_GR5_3 ((uint32_t)0x00000100) |
| #define | RI_ASCR2_GR4_1 ((uint32_t)0x00000200) |
| #define | RI_ASCR2_GR4_2 ((uint32_t)0x00000400) |
| #define | RI_ASCR2_GR4_3 ((uint32_t)0x00000800) |
| #define | RI_ASCR2_GR4_4 ((uint32_t)0x00008000) |
| #define | RI_ASCR2_CH0b ((uint32_t)0x00010000) |
| #define | RI_ASCR2_CH1b ((uint32_t)0x00020000) |
| #define | RI_ASCR2_CH2b ((uint32_t)0x00040000) |
| #define | RI_ASCR2_CH3b ((uint32_t)0x00080000) |
| #define | RI_ASCR2_CH6b ((uint32_t)0x00100000) |
| #define | RI_ASCR2_CH7b ((uint32_t)0x00200000) |
| #define | RI_ASCR2_CH8b ((uint32_t)0x00400000) |
| #define | RI_ASCR2_CH9b ((uint32_t)0x00800000) |
| #define | RI_ASCR2_CH10b ((uint32_t)0x01000000) |
| #define | RI_ASCR2_CH11b ((uint32_t)0x02000000) |
| #define | RI_ASCR2_CH12b ((uint32_t)0x04000000) |
| #define | RI_ASCR2_GR6_3 ((uint32_t)0x08000000) |
| #define | RI_ASCR2_GR6_4 ((uint32_t)0x10000000) |
| #define | RI_ASCR2_GR5_4 ((uint32_t)0x20000000) |
| #define | RI_HYSCR1_PA ((uint32_t)0x0000FFFF) |
| #define | RI_HYSCR1_PA_0 ((uint32_t)0x00000001) |
| #define | RI_HYSCR1_PA_1 ((uint32_t)0x00000002) |
| #define | RI_HYSCR1_PA_2 ((uint32_t)0x00000004) |
| #define | RI_HYSCR1_PA_3 ((uint32_t)0x00000008) |
| #define | RI_HYSCR1_PA_4 ((uint32_t)0x00000010) |
| #define | RI_HYSCR1_PA_5 ((uint32_t)0x00000020) |
| #define | RI_HYSCR1_PA_6 ((uint32_t)0x00000040) |
| #define | RI_HYSCR1_PA_7 ((uint32_t)0x00000080) |
| #define | RI_HYSCR1_PA_8 ((uint32_t)0x00000100) |
| #define | RI_HYSCR1_PA_9 ((uint32_t)0x00000200) |
| #define | RI_HYSCR1_PA_10 ((uint32_t)0x00000400) |
| #define | RI_HYSCR1_PA_11 ((uint32_t)0x00000800) |
| #define | RI_HYSCR1_PA_12 ((uint32_t)0x00001000) |
| #define | RI_HYSCR1_PA_13 ((uint32_t)0x00002000) |
| #define | RI_HYSCR1_PA_14 ((uint32_t)0x00004000) |
| #define | RI_HYSCR1_PA_15 ((uint32_t)0x00008000) |
| #define | RI_HYSCR1_PB ((uint32_t)0xFFFF0000) |
| #define | RI_HYSCR1_PB_0 ((uint32_t)0x00010000) |
| #define | RI_HYSCR1_PB_1 ((uint32_t)0x00020000) |
| #define | RI_HYSCR1_PB_2 ((uint32_t)0x00040000) |
| #define | RI_HYSCR1_PB_3 ((uint32_t)0x00080000) |
| #define | RI_HYSCR1_PB_4 ((uint32_t)0x00100000) |
| #define | RI_HYSCR1_PB_5 ((uint32_t)0x00200000) |
| #define | RI_HYSCR1_PB_6 ((uint32_t)0x00400000) |
| #define | RI_HYSCR1_PB_7 ((uint32_t)0x00800000) |
| #define | RI_HYSCR1_PB_8 ((uint32_t)0x01000000) |
| #define | RI_HYSCR1_PB_9 ((uint32_t)0x02000000) |
| #define | RI_HYSCR1_PB_10 ((uint32_t)0x04000000) |
| #define | RI_HYSCR1_PB_11 ((uint32_t)0x08000000) |
| #define | RI_HYSCR1_PB_12 ((uint32_t)0x10000000) |
| #define | RI_HYSCR1_PB_13 ((uint32_t)0x20000000) |
| #define | RI_HYSCR1_PB_14 ((uint32_t)0x40000000) |
| #define | RI_HYSCR1_PB_15 ((uint32_t)0x80000000) |
| #define | RI_HYSCR2_PC ((uint32_t)0x0000FFFF) |
| #define | RI_HYSCR2_PC_0 ((uint32_t)0x00000001) |
| #define | RI_HYSCR2_PC_1 ((uint32_t)0x00000002) |
| #define | RI_HYSCR2_PC_2 ((uint32_t)0x00000004) |
| #define | RI_HYSCR2_PC_3 ((uint32_t)0x00000008) |
| #define | RI_HYSCR2_PC_4 ((uint32_t)0x00000010) |
| #define | RI_HYSCR2_PC_5 ((uint32_t)0x00000020) |
| #define | RI_HYSCR2_PC_6 ((uint32_t)0x00000040) |
| #define | RI_HYSCR2_PC_7 ((uint32_t)0x00000080) |
| #define | RI_HYSCR2_PC_8 ((uint32_t)0x00000100) |
| #define | RI_HYSCR2_PC_9 ((uint32_t)0x00000200) |
| #define | RI_HYSCR2_PC_10 ((uint32_t)0x00000400) |
| #define | RI_HYSCR2_PC_11 ((uint32_t)0x00000800) |
| #define | RI_HYSCR2_PC_12 ((uint32_t)0x00001000) |
| #define | RI_HYSCR2_PC_13 ((uint32_t)0x00002000) |
| #define | RI_HYSCR2_PC_14 ((uint32_t)0x00004000) |
| #define | RI_HYSCR2_PC_15 ((uint32_t)0x00008000) |
| #define | RI_HYSCR2_PD ((uint32_t)0xFFFF0000) |
| #define | RI_HYSCR2_PD_0 ((uint32_t)0x00010000) |
| #define | RI_HYSCR2_PD_1 ((uint32_t)0x00020000) |
| #define | RI_HYSCR2_PD_2 ((uint32_t)0x00040000) |
| #define | RI_HYSCR2_PD_3 ((uint32_t)0x00080000) |
| #define | RI_HYSCR2_PD_4 ((uint32_t)0x00100000) |
| #define | RI_HYSCR2_PD_5 ((uint32_t)0x00200000) |
| #define | RI_HYSCR2_PD_6 ((uint32_t)0x00400000) |
| #define | RI_HYSCR2_PD_7 ((uint32_t)0x00800000) |
| #define | RI_HYSCR2_PD_8 ((uint32_t)0x01000000) |
| #define | RI_HYSCR2_PD_9 ((uint32_t)0x02000000) |
| #define | RI_HYSCR2_PD_10 ((uint32_t)0x04000000) |
| #define | RI_HYSCR2_PD_11 ((uint32_t)0x08000000) |
| #define | RI_HYSCR2_PD_12 ((uint32_t)0x10000000) |
| #define | RI_HYSCR2_PD_13 ((uint32_t)0x20000000) |
| #define | RI_HYSCR2_PD_14 ((uint32_t)0x40000000) |
| #define | RI_HYSCR2_PD_15 ((uint32_t)0x80000000) |
| #define | RI_HYSCR2_PE ((uint32_t)0x0000FFFF) |
| #define | RI_HYSCR2_PE_0 ((uint32_t)0x00000001) |
| #define | RI_HYSCR2_PE_1 ((uint32_t)0x00000002) |
| #define | RI_HYSCR2_PE_2 ((uint32_t)0x00000004) |
| #define | RI_HYSCR2_PE_3 ((uint32_t)0x00000008) |
| #define | RI_HYSCR2_PE_4 ((uint32_t)0x00000010) |
| #define | RI_HYSCR2_PE_5 ((uint32_t)0x00000020) |
| #define | RI_HYSCR2_PE_6 ((uint32_t)0x00000040) |
| #define | RI_HYSCR2_PE_7 ((uint32_t)0x00000080) |
| #define | RI_HYSCR2_PE_8 ((uint32_t)0x00000100) |
| #define | RI_HYSCR2_PE_9 ((uint32_t)0x00000200) |
| #define | RI_HYSCR2_PE_10 ((uint32_t)0x00000400) |
| #define | RI_HYSCR2_PE_11 ((uint32_t)0x00000800) |
| #define | RI_HYSCR2_PE_12 ((uint32_t)0x00001000) |
| #define | RI_HYSCR2_PE_13 ((uint32_t)0x00002000) |
| #define | RI_HYSCR2_PE_14 ((uint32_t)0x00004000) |
| #define | RI_HYSCR2_PE_15 ((uint32_t)0x00008000) |
| #define | RI_HYSCR3_PF ((uint32_t)0xFFFF0000) |
| #define | RI_HYSCR3_PF_0 ((uint32_t)0x00010000) |
| #define | RI_HYSCR3_PF_1 ((uint32_t)0x00020000) |
| #define | RI_HYSCR3_PF_2 ((uint32_t)0x00040000) |
| #define | RI_HYSCR3_PF_3 ((uint32_t)0x00080000) |
| #define | RI_HYSCR3_PF_4 ((uint32_t)0x00100000) |
| #define | RI_HYSCR3_PF_5 ((uint32_t)0x00200000) |
| #define | RI_HYSCR3_PF_6 ((uint32_t)0x00400000) |
| #define | RI_HYSCR3_PF_7 ((uint32_t)0x00800000) |
| #define | RI_HYSCR3_PF_8 ((uint32_t)0x01000000) |
| #define | RI_HYSCR3_PF_9 ((uint32_t)0x02000000) |
| #define | RI_HYSCR3_PF_10 ((uint32_t)0x04000000) |
| #define | RI_HYSCR3_PF_11 ((uint32_t)0x08000000) |
| #define | RI_HYSCR3_PF_12 ((uint32_t)0x10000000) |
| #define | RI_HYSCR3_PF_13 ((uint32_t)0x20000000) |
| #define | RI_HYSCR3_PF_14 ((uint32_t)0x40000000) |
| #define | RI_HYSCR3_PF_15 ((uint32_t)0x80000000) |
| #define | RI_HYSCR4_PG ((uint32_t)0x0000FFFF) |
| #define | RI_HYSCR4_PG_0 ((uint32_t)0x00000001) |
| #define | RI_HYSCR4_PG_1 ((uint32_t)0x00000002) |
| #define | RI_HYSCR4_PG_2 ((uint32_t)0x00000004) |
| #define | RI_HYSCR4_PG_3 ((uint32_t)0x00000008) |
| #define | RI_HYSCR4_PG_4 ((uint32_t)0x00000010) |
| #define | RI_HYSCR4_PG_5 ((uint32_t)0x00000020) |
| #define | RI_HYSCR4_PG_6 ((uint32_t)0x00000040) |
| #define | RI_HYSCR4_PG_7 ((uint32_t)0x00000080) |
| #define | RI_HYSCR4_PG_8 ((uint32_t)0x00000100) |
| #define | RI_HYSCR4_PG_9 ((uint32_t)0x00000200) |
| #define | RI_HYSCR4_PG_10 ((uint32_t)0x00000400) |
| #define | RI_HYSCR4_PG_11 ((uint32_t)0x00000800) |
| #define | RI_HYSCR4_PG_12 ((uint32_t)0x00001000) |
| #define | RI_HYSCR4_PG_13 ((uint32_t)0x00002000) |
| #define | RI_HYSCR4_PG_14 ((uint32_t)0x00004000) |
| #define | RI_HYSCR4_PG_15 ((uint32_t)0x00008000) |
| #define | TIM_CR1_CEN ((uint16_t)0x0001) |
| #define | TIM_CR1_UDIS ((uint16_t)0x0002) |
| #define | TIM_CR1_URS ((uint16_t)0x0004) |
| #define | TIM_CR1_OPM ((uint16_t)0x0008) |
| #define | TIM_CR1_DIR ((uint16_t)0x0010) |
| #define | TIM_CR1_CMS ((uint16_t)0x0060) |
| #define | TIM_CR1_CMS_0 ((uint16_t)0x0020) |
| #define | TIM_CR1_CMS_1 ((uint16_t)0x0040) |
| #define | TIM_CR1_ARPE ((uint16_t)0x0080) |
| #define | TIM_CR1_CKD ((uint16_t)0x0300) |
| #define | TIM_CR1_CKD_0 ((uint16_t)0x0100) |
| #define | TIM_CR1_CKD_1 ((uint16_t)0x0200) |
| #define | TIM_CR2_CCDS ((uint16_t)0x0008) |
| #define | TIM_CR2_MMS ((uint16_t)0x0070) |
| #define | TIM_CR2_MMS_0 ((uint16_t)0x0010) |
| #define | TIM_CR2_MMS_1 ((uint16_t)0x0020) |
| #define | TIM_CR2_MMS_2 ((uint16_t)0x0040) |
| #define | TIM_CR2_TI1S ((uint16_t)0x0080) |
| #define | TIM_SMCR_SMS ((uint16_t)0x0007) |
| #define | TIM_SMCR_SMS_0 ((uint16_t)0x0001) |
| #define | TIM_SMCR_SMS_1 ((uint16_t)0x0002) |
| #define | TIM_SMCR_SMS_2 ((uint16_t)0x0004) |
| #define | TIM_SMCR_OCCS ((uint16_t)0x0008) |
| #define | TIM_SMCR_TS ((uint16_t)0x0070) |
| #define | TIM_SMCR_TS_0 ((uint16_t)0x0010) |
| #define | TIM_SMCR_TS_1 ((uint16_t)0x0020) |
| #define | TIM_SMCR_TS_2 ((uint16_t)0x0040) |
| #define | TIM_SMCR_MSM ((uint16_t)0x0080) |
| #define | TIM_SMCR_ETF ((uint16_t)0x0F00) |
| #define | TIM_SMCR_ETF_0 ((uint16_t)0x0100) |
| #define | TIM_SMCR_ETF_1 ((uint16_t)0x0200) |
| #define | TIM_SMCR_ETF_2 ((uint16_t)0x0400) |
| #define | TIM_SMCR_ETF_3 ((uint16_t)0x0800) |
| #define | TIM_SMCR_ETPS ((uint16_t)0x3000) |
| #define | TIM_SMCR_ETPS_0 ((uint16_t)0x1000) |
| #define | TIM_SMCR_ETPS_1 ((uint16_t)0x2000) |
| #define | TIM_SMCR_ECE ((uint16_t)0x4000) |
| #define | TIM_SMCR_ETP ((uint16_t)0x8000) |
| #define | TIM_DIER_UIE ((uint16_t)0x0001) |
| #define | TIM_DIER_CC1IE ((uint16_t)0x0002) |
| #define | TIM_DIER_CC2IE ((uint16_t)0x0004) |
| #define | TIM_DIER_CC3IE ((uint16_t)0x0008) |
| #define | TIM_DIER_CC4IE ((uint16_t)0x0010) |
| #define | TIM_DIER_TIE ((uint16_t)0x0040) |
| #define | TIM_DIER_UDE ((uint16_t)0x0100) |
| #define | TIM_DIER_CC1DE ((uint16_t)0x0200) |
| #define | TIM_DIER_CC2DE ((uint16_t)0x0400) |
| #define | TIM_DIER_CC3DE ((uint16_t)0x0800) |
| #define | TIM_DIER_CC4DE ((uint16_t)0x1000) |
| #define | TIM_DIER_TDE ((uint16_t)0x4000) |
| #define | TIM_SR_UIF ((uint16_t)0x0001) |
| #define | TIM_SR_CC1IF ((uint16_t)0x0002) |
| #define | TIM_SR_CC2IF ((uint16_t)0x0004) |
| #define | TIM_SR_CC3IF ((uint16_t)0x0008) |
| #define | TIM_SR_CC4IF ((uint16_t)0x0010) |
| #define | TIM_SR_TIF ((uint16_t)0x0040) |
| #define | TIM_SR_CC1OF ((uint16_t)0x0200) |
| #define | TIM_SR_CC2OF ((uint16_t)0x0400) |
| #define | TIM_SR_CC3OF ((uint16_t)0x0800) |
| #define | TIM_SR_CC4OF ((uint16_t)0x1000) |
| #define | TIM_EGR_UG ((uint8_t)0x01) |
| #define | TIM_EGR_CC1G ((uint8_t)0x02) |
| #define | TIM_EGR_CC2G ((uint8_t)0x04) |
| #define | TIM_EGR_CC3G ((uint8_t)0x08) |
| #define | TIM_EGR_CC4G ((uint8_t)0x10) |
| #define | TIM_EGR_TG ((uint8_t)0x40) |
| #define | TIM_CCMR1_CC1S ((uint16_t)0x0003) |
| #define | TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR1_OC1FE ((uint16_t)0x0004) |
| #define | TIM_CCMR1_OC1PE ((uint16_t)0x0008) |
| #define | TIM_CCMR1_OC1M ((uint16_t)0x0070) |
| #define | TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_OC1CE ((uint16_t)0x0080) |
| #define | TIM_CCMR1_CC2S ((uint16_t)0x0300) |
| #define | TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR1_OC2FE ((uint16_t)0x0400) |
| #define | TIM_CCMR1_OC2PE ((uint16_t)0x0800) |
| #define | TIM_CCMR1_OC2M ((uint16_t)0x7000) |
| #define | TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_OC2CE ((uint16_t)0x8000) |
| #define | TIM_CCMR1_IC1PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR1_IC1F ((uint16_t)0x00F0) |
| #define | TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR1_IC2F ((uint16_t)0xF000) |
| #define | TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) |
| #define | TIM_CCMR2_CC3S ((uint16_t)0x0003) |
| #define | TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) |
| #define | TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) |
| #define | TIM_CCMR2_OC3FE ((uint16_t)0x0004) |
| #define | TIM_CCMR2_OC3PE ((uint16_t)0x0008) |
| #define | TIM_CCMR2_OC3M ((uint16_t)0x0070) |
| #define | TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_OC3CE ((uint16_t)0x0080) |
| #define | TIM_CCMR2_CC4S ((uint16_t)0x0300) |
| #define | TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) |
| #define | TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) |
| #define | TIM_CCMR2_OC4FE ((uint16_t)0x0400) |
| #define | TIM_CCMR2_OC4PE ((uint16_t)0x0800) |
| #define | TIM_CCMR2_OC4M ((uint16_t)0x7000) |
| #define | TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_OC4CE ((uint16_t)0x8000) |
| #define | TIM_CCMR2_IC3PSC ((uint16_t)0x000C) |
| #define | TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) |
| #define | TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) |
| #define | TIM_CCMR2_IC3F ((uint16_t)0x00F0) |
| #define | TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) |
| #define | TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) |
| #define | TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) |
| #define | TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) |
| #define | TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) |
| #define | TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) |
| #define | TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) |
| #define | TIM_CCMR2_IC4F ((uint16_t)0xF000) |
| #define | TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) |
| #define | TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) |
| #define | TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) |
| #define | TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) |
| #define | TIM_CCER_CC1E ((uint16_t)0x0001) |
| #define | TIM_CCER_CC1P ((uint16_t)0x0002) |
| #define | TIM_CCER_CC1NP ((uint16_t)0x0008) |
| #define | TIM_CCER_CC2E ((uint16_t)0x0010) |
| #define | TIM_CCER_CC2P ((uint16_t)0x0020) |
| #define | TIM_CCER_CC2NP ((uint16_t)0x0080) |
| #define | TIM_CCER_CC3E ((uint16_t)0x0100) |
| #define | TIM_CCER_CC3P ((uint16_t)0x0200) |
| #define | TIM_CCER_CC3NP ((uint16_t)0x0800) |
| #define | TIM_CCER_CC4E ((uint16_t)0x1000) |
| #define | TIM_CCER_CC4P ((uint16_t)0x2000) |
| #define | TIM_CCER_CC4NP ((uint16_t)0x8000) |
| #define | TIM_CNT_CNT ((uint16_t)0xFFFF) |
| #define | TIM_PSC_PSC ((uint16_t)0xFFFF) |
| #define | TIM_ARR_ARR ((uint16_t)0xFFFF) |
| #define | TIM_CCR1_CCR1 ((uint16_t)0xFFFF) |
| #define | TIM_CCR2_CCR2 ((uint16_t)0xFFFF) |
| #define | TIM_CCR3_CCR3 ((uint16_t)0xFFFF) |
| #define | TIM_CCR4_CCR4 ((uint16_t)0xFFFF) |
| #define | TIM_DCR_DBA ((uint16_t)0x001F) |
| #define | TIM_DCR_DBA_0 ((uint16_t)0x0001) |
| #define | TIM_DCR_DBA_1 ((uint16_t)0x0002) |
| #define | TIM_DCR_DBA_2 ((uint16_t)0x0004) |
| #define | TIM_DCR_DBA_3 ((uint16_t)0x0008) |
| #define | TIM_DCR_DBA_4 ((uint16_t)0x0010) |
| #define | TIM_DCR_DBL ((uint16_t)0x1F00) |
| #define | TIM_DCR_DBL_0 ((uint16_t)0x0100) |
| #define | TIM_DCR_DBL_1 ((uint16_t)0x0200) |
| #define | TIM_DCR_DBL_2 ((uint16_t)0x0400) |
| #define | TIM_DCR_DBL_3 ((uint16_t)0x0800) |
| #define | TIM_DCR_DBL_4 ((uint16_t)0x1000) |
| #define | TIM_DMAR_DMAB ((uint16_t)0xFFFF) |
| #define | TIM_OR_TI1RMP ((uint16_t)0x0003) |
| #define | TIM_OR_TI1RMP_0 ((uint16_t)0x0001) |
| #define | TIM_OR_TI1RMP_1 ((uint16_t)0x0002) |
| #define | USART_SR_PE ((uint16_t)0x0001) |
| #define | USART_SR_FE ((uint16_t)0x0002) |
| #define | USART_SR_NE ((uint16_t)0x0004) |
| #define | USART_SR_ORE ((uint16_t)0x0008) |
| #define | USART_SR_IDLE ((uint16_t)0x0010) |
| #define | USART_SR_RXNE ((uint16_t)0x0020) |
| #define | USART_SR_TC ((uint16_t)0x0040) |
| #define | USART_SR_TXE ((uint16_t)0x0080) |
| #define | USART_SR_LBD ((uint16_t)0x0100) |
| #define | USART_SR_CTS ((uint16_t)0x0200) |
| #define | USART_DR_DR ((uint16_t)0x01FF) |
| #define | USART_BRR_DIV_FRACTION ((uint16_t)0x000F) |
| #define | USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) |
| #define | USART_CR1_SBK ((uint16_t)0x0001) |
| #define | USART_CR1_RWU ((uint16_t)0x0002) |
| #define | USART_CR1_RE ((uint16_t)0x0004) |
| #define | USART_CR1_TE ((uint16_t)0x0008) |
| #define | USART_CR1_IDLEIE ((uint16_t)0x0010) |
| #define | USART_CR1_RXNEIE ((uint16_t)0x0020) |
| #define | USART_CR1_TCIE ((uint16_t)0x0040) |
| #define | USART_CR1_TXEIE ((uint16_t)0x0080) |
| #define | USART_CR1_PEIE ((uint16_t)0x0100) |
| #define | USART_CR1_PS ((uint16_t)0x0200) |
| #define | USART_CR1_PCE ((uint16_t)0x0400) |
| #define | USART_CR1_WAKE ((uint16_t)0x0800) |
| #define | USART_CR1_M ((uint16_t)0x1000) |
| #define | USART_CR1_UE ((uint16_t)0x2000) |
| #define | USART_CR1_OVER8 ((uint16_t)0x8000) |
| #define | USART_CR2_ADD ((uint16_t)0x000F) |
| #define | USART_CR2_LBDL ((uint16_t)0x0020) |
| #define | USART_CR2_LBDIE ((uint16_t)0x0040) |
| #define | USART_CR2_LBCL ((uint16_t)0x0100) |
| #define | USART_CR2_CPHA ((uint16_t)0x0200) |
| #define | USART_CR2_CPOL ((uint16_t)0x0400) |
| #define | USART_CR2_CLKEN ((uint16_t)0x0800) |
| #define | USART_CR2_STOP ((uint16_t)0x3000) |
| #define | USART_CR2_STOP_0 ((uint16_t)0x1000) |
| #define | USART_CR2_STOP_1 ((uint16_t)0x2000) |
| #define | USART_CR2_LINEN ((uint16_t)0x4000) |
| #define | USART_CR3_EIE ((uint16_t)0x0001) |
| #define | USART_CR3_IREN ((uint16_t)0x0002) |
| #define | USART_CR3_IRLP ((uint16_t)0x0004) |
| #define | USART_CR3_HDSEL ((uint16_t)0x0008) |
| #define | USART_CR3_NACK ((uint16_t)0x0010) |
| #define | USART_CR3_SCEN ((uint16_t)0x0020) |
| #define | USART_CR3_DMAR ((uint16_t)0x0040) |
| #define | USART_CR3_DMAT ((uint16_t)0x0080) |
| #define | USART_CR3_RTSE ((uint16_t)0x0100) |
| #define | USART_CR3_CTSE ((uint16_t)0x0200) |
| #define | USART_CR3_CTSIE ((uint16_t)0x0400) |
| #define | USART_CR3_ONEBIT ((uint16_t)0x0800) |
| #define | USART_GTPR_PSC ((uint16_t)0x00FF) |
| #define | USART_GTPR_PSC_0 ((uint16_t)0x0001) |
| #define | USART_GTPR_PSC_1 ((uint16_t)0x0002) |
| #define | USART_GTPR_PSC_2 ((uint16_t)0x0004) |
| #define | USART_GTPR_PSC_3 ((uint16_t)0x0008) |
| #define | USART_GTPR_PSC_4 ((uint16_t)0x0010) |
| #define | USART_GTPR_PSC_5 ((uint16_t)0x0020) |
| #define | USART_GTPR_PSC_6 ((uint16_t)0x0040) |
| #define | USART_GTPR_PSC_7 ((uint16_t)0x0080) |
| #define | USART_GTPR_GT ((uint16_t)0xFF00) |
| #define | USB_EP0R_EA ((uint16_t)0x000F) |
| #define | USB_EP0R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP0R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP0R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP0R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP0R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP0R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP0R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP0R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP0R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP1R_EA ((uint16_t)0x000F) |
| #define | USB_EP1R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP1R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP1R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP1R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP1R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP1R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP1R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP1R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP1R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP2R_EA ((uint16_t)0x000F) |
| #define | USB_EP2R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP2R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP2R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP2R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP2R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP2R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP2R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP2R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP2R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP3R_EA ((uint16_t)0x000F) |
| #define | USB_EP3R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP3R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP3R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP3R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP3R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP3R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP3R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP3R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP3R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP4R_EA ((uint16_t)0x000F) |
| #define | USB_EP4R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP4R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP4R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP4R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP4R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP4R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP4R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP4R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP4R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP5R_EA ((uint16_t)0x000F) |
| #define | USB_EP5R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP5R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP5R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP5R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP5R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP5R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP5R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP5R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP5R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP6R_EA ((uint16_t)0x000F) |
| #define | USB_EP6R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP6R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP6R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP6R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP6R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP6R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP6R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP6R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP6R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_EP7R_EA ((uint16_t)0x000F) |
| #define | USB_EP7R_STAT_TX ((uint16_t)0x0030) |
| #define | USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) |
| #define | USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) |
| #define | USB_EP7R_DTOG_TX ((uint16_t)0x0040) |
| #define | USB_EP7R_CTR_TX ((uint16_t)0x0080) |
| #define | USB_EP7R_EP_KIND ((uint16_t)0x0100) |
| #define | USB_EP7R_EP_TYPE ((uint16_t)0x0600) |
| #define | USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) |
| #define | USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) |
| #define | USB_EP7R_SETUP ((uint16_t)0x0800) |
| #define | USB_EP7R_STAT_RX ((uint16_t)0x3000) |
| #define | USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) |
| #define | USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) |
| #define | USB_EP7R_DTOG_RX ((uint16_t)0x4000) |
| #define | USB_EP7R_CTR_RX ((uint16_t)0x8000) |
| #define | USB_CNTR_FRES ((uint16_t)0x0001) |
| #define | USB_CNTR_PDWN ((uint16_t)0x0002) |
| #define | USB_CNTR_LP_MODE ((uint16_t)0x0004) |
| #define | USB_CNTR_FSUSP ((uint16_t)0x0008) |
| #define | USB_CNTR_RESUME ((uint16_t)0x0010) |
| #define | USB_CNTR_ESOFM ((uint16_t)0x0100) |
| #define | USB_CNTR_SOFM ((uint16_t)0x0200) |
| #define | USB_CNTR_RESETM ((uint16_t)0x0400) |
| #define | USB_CNTR_SUSPM ((uint16_t)0x0800) |
| #define | USB_CNTR_WKUPM ((uint16_t)0x1000) |
| #define | USB_CNTR_ERRM ((uint16_t)0x2000) |
| #define | USB_CNTR_PMAOVRM ((uint16_t)0x4000) |
| #define | USB_CNTR_CTRM ((uint16_t)0x8000) |
| #define | USB_ISTR_EP_ID ((uint16_t)0x000F) |
| #define | USB_ISTR_DIR ((uint16_t)0x0010) |
| #define | USB_ISTR_ESOF ((uint16_t)0x0100) |
| #define | USB_ISTR_SOF ((uint16_t)0x0200) |
| #define | USB_ISTR_RESET ((uint16_t)0x0400) |
| #define | USB_ISTR_SUSP ((uint16_t)0x0800) |
| #define | USB_ISTR_WKUP ((uint16_t)0x1000) |
| #define | USB_ISTR_ERR ((uint16_t)0x2000) |
| #define | USB_ISTR_PMAOVR ((uint16_t)0x4000) |
| #define | USB_ISTR_CTR ((uint16_t)0x8000) |
| #define | USB_FNR_FN ((uint16_t)0x07FF) |
| #define | USB_FNR_LSOF ((uint16_t)0x1800) |
| #define | USB_FNR_LCK ((uint16_t)0x2000) |
| #define | USB_FNR_RXDM ((uint16_t)0x4000) |
| #define | USB_FNR_RXDP ((uint16_t)0x8000) |
| #define | USB_DADDR_ADD ((uint8_t)0x7F) |
| #define | USB_DADDR_ADD0 ((uint8_t)0x01) |
| #define | USB_DADDR_ADD1 ((uint8_t)0x02) |
| #define | USB_DADDR_ADD2 ((uint8_t)0x04) |
| #define | USB_DADDR_ADD3 ((uint8_t)0x08) |
| #define | USB_DADDR_ADD4 ((uint8_t)0x10) |
| #define | USB_DADDR_ADD5 ((uint8_t)0x20) |
| #define | USB_DADDR_ADD6 ((uint8_t)0x40) |
| #define | USB_DADDR_EF ((uint8_t)0x80) |
| #define | USB_BTABLE_BTABLE ((uint16_t)0xFFF8) |
| #define | USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) |
| #define | USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) |
| #define | USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) |
| #define | USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) |
| #define | USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) |
| #define | USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) |
| #define | USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) |
| #define | USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) |
| #define | USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) |
| #define | USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) |
| #define | USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) |
| #define | USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) |
| #define | USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) |
| #define | USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) |
| #define | USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) |
| #define | USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) |
| #define | USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) |
| #define | USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) |
| #define | USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) |
| #define | USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) |
| #define | USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) |
| #define | WWDG_CR_T ((uint8_t)0x7F) |
| #define | WWDG_CR_T0 ((uint8_t)0x01) |
| #define | WWDG_CR_T1 ((uint8_t)0x02) |
| #define | WWDG_CR_T2 ((uint8_t)0x04) |
| #define | WWDG_CR_T3 ((uint8_t)0x08) |
| #define | WWDG_CR_T4 ((uint8_t)0x10) |
| #define | WWDG_CR_T5 ((uint8_t)0x20) |
| #define | WWDG_CR_T6 ((uint8_t)0x40) |
| #define | WWDG_CR_WDGA ((uint8_t)0x80) |
| #define | WWDG_CFR_W ((uint16_t)0x007F) |
| #define | WWDG_CFR_W0 ((uint16_t)0x0001) |
| #define | WWDG_CFR_W1 ((uint16_t)0x0002) |
| #define | WWDG_CFR_W2 ((uint16_t)0x0004) |
| #define | WWDG_CFR_W3 ((uint16_t)0x0008) |
| #define | WWDG_CFR_W4 ((uint16_t)0x0010) |
| #define | WWDG_CFR_W5 ((uint16_t)0x0020) |
| #define | WWDG_CFR_W6 ((uint16_t)0x0040) |
| #define | WWDG_CFR_WDGTB ((uint16_t)0x0180) |
| #define | WWDG_CFR_WDGTB0 ((uint16_t)0x0080) |
| #define | WWDG_CFR_WDGTB1 ((uint16_t)0x0100) |
| #define | WWDG_CFR_EWI ((uint16_t)0x0200) |
| #define | WWDG_SR_EWIF ((uint8_t)0x01) |
| #define | SysTick_CTRL_ENABLE ((uint32_t)0x00000001) |
| #define | SysTick_CTRL_TICKINT ((uint32_t)0x00000002) |
| #define | SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) |
| #define | SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) |
| #define | SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) |
| #define | SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) |
| #define | SysTick_CALIB_SKEW ((uint32_t)0x40000000) |
| #define | SysTick_CALIB_NOREF ((uint32_t)0x80000000) |
| #define | NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) |
| #define | NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) |
| #define | NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) |
| #define | NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) |
| #define | NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) |
| #define | NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) |
| #define | NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) |
| #define | NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) |
| #define | NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) |
| #define | NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) |
| #define | NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) |
| #define | NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) |
| #define | NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) |
| #define | NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) |
| #define | NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) |
| #define | NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) |
| #define | NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) |
| #define | NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) |
| #define | NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) |
| #define | NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) |
| #define | NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) |
| #define | NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) |
| #define | NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) |
| #define | NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) |
| #define | NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) |
| #define | NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) |
| #define | NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) |
| #define | NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) |
| #define | NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) |
| #define | NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) |
| #define | NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) |
| #define | NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) |
| #define | NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) |
| #define | NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) |
| #define | NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) |
| #define | NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) |
| #define | NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) |
| #define | NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) |
| #define | NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) |
| #define | NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) |
| #define | NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) |
| #define | NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) |
| #define | NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) |
| #define | NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) |
| #define | NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) |
| #define | NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) |
| #define | NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) |
| #define | NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) |
| #define | NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) |
| #define | NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) |
| #define | NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) |
| #define | NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) |
| #define | NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) |
| #define | NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) |
| #define | NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) |
| #define | NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) |
| #define | NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) |
| #define | NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) |
| #define | NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) |
| #define | NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) |
| #define | NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) |
| #define | NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) |
| #define | NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) |
| #define | NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) |
| #define | NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) |
| #define | NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) |
| #define | NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) |
| #define | NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) |
| #define | NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) |
| #define | NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) |
| #define | NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) |
| #define | SCB_CPUID_REVISION ((uint32_t)0x0000000F) |
| #define | SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) |
| #define | SCB_CPUID_Constant ((uint32_t)0x000F0000) |
| #define | SCB_CPUID_VARIANT ((uint32_t)0x00F00000) |
| #define | SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) |
| #define | SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) |
| #define | SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) |
| #define | SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) |
| #define | SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) |
| #define | SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) |
| #define | SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) |
| #define | SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) |
| #define | SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) |
| #define | SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) |
| #define | SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) |
| #define | SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) |
| #define | SCB_VTOR_TBLBASE ((uint32_t)0x20000000) |
| #define | SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) |
| #define | SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) |
| #define | SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) |
| #define | SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) |
| #define | SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) |
| #define | SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) |
| #define | SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) |
| #define | SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) |
| #define | SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) |
| #define | SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) |
| #define | SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) |
| #define | SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) |
| #define | SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) |
| #define | SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) |
| #define | SCB_SCR_SLEEPDEEP ((uint8_t)0x04) |
| #define | SCB_SCR_SEVONPEND ((uint8_t)0x10) |
| #define | SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) |
| #define | SCB_CCR_USERSETMPEND ((uint16_t)0x0002) |
| #define | SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) |
| #define | SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) |
| #define | SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) |
| #define | SCB_CCR_STKALIGN ((uint16_t)0x0200) |
| #define | SCB_SHPR_PRI_N ((uint32_t)0x000000FF) |
| #define | SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) |
| #define | SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) |
| #define | SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) |
| #define | SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) |
| #define | SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) |
| #define | SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) |
| #define | SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) |
| #define | SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) |
| #define | SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) |
| #define | SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) |
| #define | SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) |
| #define | SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) |
| #define | SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) |
| #define | SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) |
| #define | SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) |
| #define | SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) |
| #define | SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) |
| #define | SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) |
| #define | SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) |
| #define | SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) |
| #define | SCB_CFSR_MSTKERR ((uint32_t)0x00000010) |
| #define | SCB_CFSR_MMARVALID ((uint32_t)0x00000080) |
| #define | SCB_CFSR_IBUSERR ((uint32_t)0x00000100) |
| #define | SCB_CFSR_PRECISERR ((uint32_t)0x00000200) |
| #define | SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) |
| #define | SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) |
| #define | SCB_CFSR_STKERR ((uint32_t)0x00001000) |
| #define | SCB_CFSR_BFARVALID ((uint32_t)0x00008000) |
| #define | SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) |
| #define | SCB_CFSR_INVSTATE ((uint32_t)0x00020000) |
| #define | SCB_CFSR_INVPC ((uint32_t)0x00040000) |
| #define | SCB_CFSR_NOCP ((uint32_t)0x00080000) |
| #define | SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) |
| #define | SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) |
| #define | SCB_HFSR_VECTTBL ((uint32_t)0x00000002) |
| #define | SCB_HFSR_FORCED ((uint32_t)0x40000000) |
| #define | SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) |
| #define | SCB_DFSR_HALTED ((uint8_t)0x01) |
| #define | SCB_DFSR_BKPT ((uint8_t)0x02) |
| #define | SCB_DFSR_DWTTRAP ((uint8_t)0x04) |
| #define | SCB_DFSR_VCATCH ((uint8_t)0x08) |
| #define | SCB_DFSR_EXTERNAL ((uint8_t)0x10) |
| #define | SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) |
| #define | SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) |
1.8.18